Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2001-02-16
2003-04-08
Nguyen, George (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S528000, C451S289000, C451S529000
Reexamination Certificate
active
06544107
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a semiconductor wafer polishing pad and, more specifically, to a composite polishing pad for use in a chemical-mechanical polishing (CMP) process.
BACKGROUND OF THE INVENTION
In the fabrication of semiconductor components, the various devices are formed in layers upon an underlying substrate, such as silicon. In such semiconductor components, it is desirable that all layers, including insulating layers, have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces.
Conventional chemical/mechanical polishing (CMP) has been developed for providing smooth semiconductor topographies. Typically, a given semiconductor wafer may be planarized several times, such as upon completion of each metal layer.
The CMP process involves using a wafer carrier to hold, and optionally rotate, a thin, reasonably flat, semiconductor wafer against a rotating polishing pad. The wafer may be repositioned radially within a set range as the polishing pad is rotated across the surface of the wafer. The polishing surface of the polishing pad, which conventionally includes a polyurethane material affixed to a platen, is wetted by a chemical slurry, under controlled chemical, pressure, and temperature conditions. The chemical slurry contains selected chemicals which etch or oxidize selected surfaces of the wafer during the CMP process in preparation for their removal.
Additionally, the slurry contains a polishing agent, such as alumina ceria or silica, that is used as the abrasive material for the mechanical removal of the semiconductor material. The combination of chemical and mechanical removal of material during the polishing process is used to achieve overall planarity of the polished surface of the semiconductor wafer. To this end, the uniform removal of material has become increasingly important in today's submicron technologies where the layers between device and metal levels are constantly getting thinner.
Unfortunately, in commercial wafer polishing operations, despite precautions to the contrary, the rate of material removal is not uniform across the entire wafer surface. Specifically, a wafer that does not evidence good planarity of the individual dies located therein is said to evidence poor “within-die” control. However, even if the wafer evidences good within-die control, if that wafer does not evidence uniform planarity from die to die, across its entire surface, it is said to have poor “within-wafer” control. For example, even though the wafer carrier is made relatively flat and rigid so as to apply a uniform downward pressure across the backside of the wafer, the wafer still has a tendency to distort during the polishing process as it is pressed onto the polishing pad. This often results in the outer annular edge region of the wafer showing evidence of decreased material removal compared to the inner portions of the wafer. This, in turn, introduces wafer non-uniformities, decreasing within-wafer uniformity.
Due to differences in polishing characteristics at the edge of the wafer compared to the center regions of the wafer, there is an “edge exclusion” for uniformity achievable across the wafer. Typically, the uniformity for planarization within a die and across the wafer are achievable within acceptable limits extendable to within 6-10 mm for the outer edge of a typical eight inch wafer. This edge exclusion is a result of the wafer carrier and polishing pad dynamic interaction that is directly related to the polishing process parameters (such as applied downforce, relative platen speed, etc.) during CMP.
Due to this reason, the edge region of the wafer often reaches the point where devices located along the edge region are less desirable, or in many cases unuseable. There is an increasing emphasis among manufacturers of semiconductor devices that the lost use of the edge area (“edge exclusion”) be reduced. Due to the high price of semiconductor wafers, such reduction has significant economic effects. As semiconductor devices become larger, edge exclusion will continue to play a role in reducing the number of devices that can be obtained from a semiconductor wafer.
Perhaps the primary factor preventing uniform polishing from being obtained at the outer edge of the wafer is considered to be the polishing pad. Commercially available polishing pads are available in varying degrees of hardness or “compressibility.” Softer pads having a higher compression rate more easily conform to the different features on the wafer and tend to achieve good within-wafer planarity. However, because of their tendency to distort to conform to the varying features, softer pads fail to provide good local planarity, resulting in poor within-die control. On the other hand, harder pads having a lesser compression rate, conform less to the various features on the wafer surface and tend to achieve good within-die control. However, the good within-die planarity obtained is usually at the expense of uniform planarity across the entire wafer, primarily at the outer edge of the wafer, resulting in poor within-wafer control.
In the prior art, composite pads have been developed to combine the best characteristics of soft and hard pads. Composite polishing pads use vertical stacking or “sandwiching” of hard and soft layers in an attempt to combine the within-die control of harder pads with the within-wafer control of softer pads. However, even when such composite polishing pads are compressed by a wafer during polishing, the pad surface may still become deformed, taking on a curved shape, at the outer portion that corresponds with the edge of the wafer. This results in the degree of compression varying continuously from maximum compression to near non-compression outward from the center of the pad. Consequently, the contact pressure of the wafer applied to the polishing pad gradually decreases as the distance from the wafer center increases.
When a composite polishing pad with a relatively “hard pad” characteristic is utilized, the planarization capability can be optimized for the center regions of the wafer. However, the outer edge of the wafer (extending well beyond the 6-10 mm edge exclusion region) can witness a significantly lower amount of polishing due to the reduced polishing pad deformation at the wafer outer edge. In fact, it is very possible that within the 6-10 mm outer edge of the wafer, the polishing pad may not be contacting the wafer at all.
Likewise, when a composite polishing pad with a relatively “soft pad” characteristic is utilized, the overall planarity across the wafer is severely degraded, even though the removal amount on the outer edge of the wafer may be raised. Clearly, with the use of so-called “sandwiched” or composited polishing pads within-die planarity is at the expense of within-wafer uniformity, and vice-versa. In either case, the outer edge of the wafer suffers severely due to poor uniformity or within-die planarity resulting in an overall reduction in chip yield.
Accordingly, what is needed in the art is a semiconductor wafer polishing pad that effectively achieves both within-die and within-wafer planarity.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a composite polishing pad. In an advantageous embodiment, the composite polishing pad includes a polishing pad member comprising a material having a predetermined hardness and an annular support member underlying a periphery of the polishing pad member, the annular support member having a hardness less than the predetermined hardness of the polishing pad member.
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Misra Sudhanshu
Roy Pradip K.
Agere Systems Inc.
Nguyen George
LandOfFree
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