Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Patent
1998-12-18
2000-02-01
Hardy, David B.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
257781, H01L 2941
Patent
active
060206470
ABSTRACT:
Disclosed is a semiconductor chip and method for making a semiconductor chip having strategically placed composite metallization. The semiconductor chip includes a topmost metallization layer that defines a plurality of patterned features including a plurality of input/output metallization pads for receiving an associated plurality of gold bonding wires. An inter-metal oxide layer that is defined under the topmost metallization layer. The semiconductor chip further includes an underlying metallization layer that is defined under the inter-metal oxide layer in order to electrically isolate the topmost metallization layer from the underlying metallization layer. The underlying metallization has a plurality of patterned features, and portions of the plurality of patterned features lie at least partially in locations that are underlying the plurality of input/output metallization pads. The portions of the plurality of patterned features are composite metallization regions that have a plurality of deformation preventing oxide patterns that are resistant to compression force induced plastic deformation that occurs when the plurality of gold bonding wires are applied.
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Bothra Subhas
Pramanik Dipu
Shu William Kuang-Hua
Skala Stephen L.
Hardy David B.
VLSI Technology Inc.
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