Composite memory having a bridging device for connecting...

Static information storage and retrieval – Format or disposition of elements

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S063000, C365S191000

Reexamination Certificate

active

07957173

ABSTRACT:
A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.

REFERENCES:
patent: 4174536 (1979-11-01), Misunas et al.
patent: 4613953 (1986-09-01), Bush
patent: 4899316 (1990-02-01), Nagami
patent: 5038299 (1991-08-01), Maeda
patent: 5204669 (1993-04-01), Dorfe et al.
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5440694 (1995-08-01), Nakajima
patent: 5636342 (1997-06-01), Jeffries
patent: 5729683 (1998-03-01), Le et al.
patent: 5740379 (1998-04-01), Hartwig
patent: 5761146 (1998-06-01), Yoo et al.
patent: 5771199 (1998-06-01), Lee
patent: 5777488 (1998-07-01), Dryer et al.
patent: 5778419 (1998-07-01), Hansen et al.
patent: 5794000 (1998-08-01), Furuta
patent: 5802399 (1998-09-01), Yumoto et al.
patent: 5802555 (1998-09-01), Shigeeda
patent: 5806070 (1998-09-01), Norman et al.
patent: 5828899 (1998-10-01), Richard et al.
patent: 5859809 (1999-01-01), Kim
patent: 5862154 (1999-01-01), Pawlowski
patent: 5900021 (1999-05-01), Tiede et al.
patent: 5937206 (1999-08-01), Nakamura
patent: 5941941 (1999-08-01), Hasegawa
patent: 5941974 (1999-08-01), Babin
patent: 5953538 (1999-09-01), Duncan
patent: 5982309 (1999-11-01), Xi et al.
patent: 6002638 (1999-12-01), John
patent: 6009479 (1999-12-01), Jeffries
patent: 6144576 (2000-11-01), Leddige et al.
patent: 6148363 (2000-11-01), Lofgren et al.
patent: 6212591 (2001-04-01), Kaplinsky
patent: 6317350 (2001-11-01), Pereira et al.
patent: 6317352 (2001-11-01), Halbert et al.
patent: 6317812 (2001-11-01), Lofgren et al.
patent: 6453365 (2002-09-01), Habot
patent: 6567904 (2003-05-01), Khandekar et al.
patent: 6658509 (2003-12-01), Bonella et al.
patent: 6658582 (2003-12-01), Han
patent: 6680904 (2004-01-01), Kaplan et al.
patent: 6697906 (2004-02-01), Ayukawa
patent: 6763426 (2004-07-01), James et al.
patent: 6766411 (2004-07-01), Goldshlag
patent: 6768431 (2004-07-01), Chiang
patent: 6792003 (2004-09-01), Potluri et al.
patent: 6807106 (2004-10-01), Gonzales et al.
patent: 6919736 (2005-07-01), Agrawal et al.
patent: 6928501 (2005-08-01), Andreas et al.
patent: 6944697 (2005-09-01), Andreas
patent: 6950325 (2005-09-01), Chen
patent: 6961882 (2005-11-01), Manfred et al.
patent: 6996644 (2006-02-01), Schoch et al.
patent: 7031221 (2006-04-01), Mooney et al.
patent: 7093076 (2006-08-01), Kyung
patent: 7130958 (2006-10-01), Chou et al.
patent: 7177170 (2007-02-01), Gomm
patent: 7599975 (2009-10-01), Donovan
patent: 2002/0103945 (2002-08-01), Owen
patent: 2002/0161941 (2002-10-01), Chue et al.
patent: 2002/0188781 (2002-12-01), Schoch et al.
patent: 2003/0163606 (2003-08-01), Fukaishi et al.
patent: 2004/0001380 (2004-01-01), Beca et al.
patent: 2004/0186948 (2004-09-01), Lofgren et al.
patent: 2004/0186956 (2004-09-01), Perego et al.
patent: 2004/0230738 (2004-11-01), Lim et al.
patent: 2004/0236892 (2004-11-01), Zhu
patent: 2005/0086595 (2005-04-01), Campbell
patent: 2005/0160218 (2005-07-01), See et al.
patent: 2005/0213421 (2005-09-01), Polizzi et al.
patent: 2005/0262289 (2005-11-01), Okuda
patent: 2006/0050594 (2006-03-01), Park
patent: 2006/0248305 (2006-11-01), Fang et al.
patent: 2007/0038852 (2007-02-01), Bovino et al.
patent: 2007/0076479 (2007-04-01), Kim et al.
patent: 2007/0076502 (2007-04-01), Pyeon et al.
patent: 2007/0109833 (2007-05-01), Pyeon et al.
patent: 2007/0143677 (2007-06-01), Pyeon et al.
patent: 2007/0153576 (2007-07-01), Oh et al.
patent: 2007/0157000 (2007-07-01), Qawami et al.
patent: 2007/0233903 (2007-10-01), Pyeon
patent: 2007/0234071 (2007-10-01), Pyeon
patent: 2008/0016269 (2008-01-01), Chow et al.
patent: 2008/0049505 (2008-02-01), Kim et al.
patent: 2008/0052449 (2008-02-01), Kim et al.
patent: 2008/0080492 (2008-04-01), Pyeon et al.
patent: 2008/0123423 (2008-05-01), Kim
patent: 2008/0155219 (2008-06-01), Pyeon et al.
patent: 2008/0155370 (2008-06-01), Kadomatsu
patent: 2008/0198682 (2008-08-01), Pyeon
patent: 2008/0201548 (2008-08-01), Przybylski et al.
patent: 2008/0205187 (2008-08-01), Pyeon
patent: 2008/0215778 (2008-09-01), Sumi
patent: 2008/0235443 (2008-09-01), Chow
patent: 2009/0021992 (2009-01-01), Oh
patent: 2009/0039927 (2009-02-01), Gillingham et al.
patent: 2009/0063786 (2009-03-01), Oh
patent: 2009/0103378 (2009-04-01), Schuetz et al.
patent: 2009/0129184 (2009-05-01), Schuetz
patent: 2009/0154285 (2009-06-01), Pyeon
patent: 2009/0154629 (2009-06-01), Pyeon et al.
patent: 2010/0091538 (2010-04-01), Kim et al.
patent: 2310080 (1999-05-01), None
patent: 2006004166 (2006-01-01), None
patent: WO 2006038811 (2006-04-01), None
Samsung, “1G×8 Bit/2G×8 Bit NAND Flash Memory”, K9F8G08UXM, Technical Specification, Samsung Electronics, Mar. 31, 2007, pp. 1-54.
Lee, S. et al., “A 3.3V 4Gb Four-Level NAND Flash Memory with 90nm CMOS Technology”, ISSCC 2004/Session 2Non-Volatile Memory/2.7, IEEE International Solid-State Circuits Conference, Feb. 15-19, 2004,Digest of Technical Papers, (10 pages), vol. 1, XP010722148, ISBN: 0-7803-8267-6.
PCT/US2008/054307, Partial Search Annex to Form PCT/ISA/206, 5 pages, Oct. 1, 2008.
PCT Patent Application No. PCT/CA2009/001451, Search Report dated Dec. 17, 2009, p. 2.
Shirota, R., et al., “A 2.3um2 Memory Cell Structure for 16Mb NAND EEPROMs”, International Electron Devices Meeting 1990, Technical Digest, Dec. 1990, pp. 103-106.
Atmel, “8-megabit 2.5-volt Only or 2.7-volt Only DataFlash®,” Technical Specification, Atmel, Rev. 2225H-DFLSH, Oct. 2004.
“16 Mbit SPI Serial Flash,” Preliminary Specification, Silicon Storage Technology Inc., Apr. 2005, 28 pages.
Hara, T. et al., “A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology”, ISSCC Session 2 Non-Volatile Memory 2.1, IEEE International Solid-State Circuits Conference, Feb. 2005, pp. 44, 45 and 584.
Byeon, D. et al., “An 8Gb Multi-Level NAND Flash Memory with 63nm STI CMOS Process Technology”, ISSCC Session 2 Non-Volatile Memory 2.2, IEEE International Solid-State Circuits Conference, Feb. 2005, pp. 46 and 47.
Tanzawa, T. et al., “Circuit Techniques for a 1.8-V-Only NAND Flash Memory”, IEEE Journal of Solid-State Circuits, vol. 37, No. 1, Jan. 2002, pp. 84-89.
Saito S., et al., “A Programmable 80ns 1Mb CMOS EPROM”, IEEE ISSCC Digest of Technical Papers, Feb. 14, 1985, pp. 176-177, 340.
Momodomi, M. et al., “A 4-Mb NAND EEPROM with tight programmed Vt Distribution”, IEEE Journal of Solid-State Circuits, vol. 26, Issue 4, Apr. 1991, pp. 492-496.
Ohtsuka, N. et al., “A 4-Mbit CMOS EPROM”, IEEE Journal of Solid-State Circuits, vol. 22, Issue 5, Oct. 1987, pp. 669-675.
Kim, et al. “A 120-mm2 64-Mb NAND Flash Memory Archieving 180 ns/Byte Effective Program Speed,” IEEE Journal of Solid-State Circuits, vol. 32, No. 5, May 1977, pp. 670-680.
Suh, K. et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1149-1156.
Takeuchi, K. et al., “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories”, IEEE Journal of Solid-State Circuits, vol. 33, Issue 8, Aug. 1998, pp. 1228-1238.
Tanzawa T., et al., “A dynamic analysis of the Dickson charge pump circuit;” IEEE J. Solid-S

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Composite memory having a bridging device for connecting... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Composite memory having a bridging device for connecting..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Composite memory having a bridging device for connecting... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2638832

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.