Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-06-27
2002-12-10
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S760000, C257S411000
Reexamination Certificate
active
06492731
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the formation of low dielectric constant (low k) dielectric material for integrated circuit structures. More particularly, this invention relates to the formation of a composite layer of low dielectric material for integrated circuit structures comprising upper and lower conformal barrier layers of low k dielectric material with a low k center layer of carbon-doped dielectric material having good gap filling capabilities.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the width of metal interconnects or lines and the horizontal spacing between such metal lines on any particular level of such interconnects have become smaller and smaller. As a result, horizontal capacitance has increased between such conductive elements. This increase in capacitance, together with the vertical capacitance which exists between metal lines on different layers, results in loss of speed and increased cross-talk. As a result, reduction of such capacitance, particularly horizontal capacitance, has received much attention. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The Trikon process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which i annealed at 400° C. to remove moisture. The article goes on to state that beyond methyl silane, studies show a possible k of 2.75 using dimethyl silane in the Trikon process. The Peters article further states that in high density plasma CVD (HDP-CVD), dielectric material formed from methyl silane or dimethyl silane and O
2
can provide a k as low as 2.75.
The use of this type of low k carbon-doped silicon oxide dielectric material has been found to have good gap filling characteristics, resulting in the formation of void-free filling of the high aspect ratio space between parallel closely spaced apart metal lines with dielectric material having a lower dielectric constant than that of convention silicon oxide, thereby resulting in a substantial lowering of the horizontal capacitance between such adjacent metal lines on the same metal wiring level.
However, the substitution of such low k carbon-doped silicon oxide dielectric materials for conventional silicon oxide insulation has not been without its own problems. Formation of the low k carbon doped silicon oxide dielectric material by the Trikon process is much slower than the conventional formation of undoped silicon oxide dielectric material. For example, in the time it takes to form a layer of low k carbon-doped silicon oxide dielectric material by the Trikon process on a single wafer, it may be possible to deposit a conventional silicon oxide dielectric layer of the same thickness on as many as 5 wafers.
However, even more importantly, it has been found that the subsequent formation of vias, or contact openings, through such low k carbon-doped silicon oxide dielectric material to the underlying conductive portions such as metal lines, or contacts on an active device, can contribute to a phenomena known as via poisoning wherein filler material subsequently deposited in the via, such as a titanium nitride liner and tungsten filler material, fails to adhere to the via surfaces.
For example, contact openings or vias are usually etched in the low k carbon-doped silicon oxide dielectric layer through a photoresist mask. When the photoresist mask used to form the vias is subsequently removed by an ashing process, damage can occur to the newly formed via surfaces of the low k carbon-doped silicon oxide dielectric material resulting in such via poisoning. Apparently the presence of carbon in the low k carbon-doped silicon oxide dielectric material formed by the Trikon process increases the porosity of the low k carbon-doped dielectric material, thus rendering the material more susceptible to damage during subsequent processing of the structure.
It has also been proposed to deposit low k silicon oxide dielectric material by other processes such as by plasma enhanced chemical vapor deposition (PECVD), using CH
4
and/or C
4
F
8
and/or silicon tetrafluoride (SiF
4
) with a mixture of silane, O
2
, and argon gases. Plasma enhanced chemical vapor deposition (PECVD) is described more fully by Wolf and Tauber in “Silicon Processing for the VSLI Era”, Volume 1-Process Technology (1986), at pages 171-174 .
While the formation of a low k silicon oxide dielectric material by PECVD is much faster than the formation of the same thickness low k carbon-doped silicon oxide dielectric layer by the Trikon (i.e., at rates approaching the deposition rate of conventional silicon oxide), low k silicon oxide dielectric material deposited by PECVD has poor gap filling characteristics in high aspect ratio regions, resulting in the formation of voids in the dielectric materials deposited by PECVD in the spaces between the closely spaced apart metal lines in such structures.
Therefore, the formation of low k carbon-doped silicon oxide dielectric material is the preferred material for use as electrical insulation between horizontally spaced apart metal lines, and between layers of metal lines to provide low capacitance between such metal lines or other conductive portions of the integrated circuit structure. However, the previously discussed susceptibility of the low k silicon-doped silicon oxide dielectric material to subsequent damage, such as during the removal of photoresist masks after formation of a via pattern in the low k material, or reaction to oxide layers or metal lines beneath the low k dielectric materials, has resulted in the use of barrier layers of dielectric material formed above and below the low k layer of dielectric material to respectively protect the upper and low surfaces of the low k silicon doped silicon oxide dielectric material.
Such barrier layers, while successfully fulfilling their function of protecting the layer of low k carbon-doped silicon oxide dielectric material, are formed of conventional dielectric material such as conventional silicon oxide. The presence of such conventional high dielectric constant material, therefore, detracts from the goal of separating the metal lines from one another, both vertically and horizontally, by electrical insulation comprising low k dielectric material to reduce the capacitance between the metal lines.
To avoid the deleterious effects of using such barrier layers of high k dielectric material, the barrier layers have been formed as thin as possible, ranging in thickness from a minimum thickness of about 50 nanometers (nm) which is sufficient to provide the desired minimum barrier up to a maximum thickness of about 500 nm. The use of thicknesses greater than the minimum needed to protect the low k carbon-doped silicon oxide dielectric material during further processing or reaction with underlying oxide layers and metal lines can have an adverse effect on the overall capacitance of the structure, since the barrier layers are not formed of low k dielectric material.
While such use of very thin barrier layers of conventional (non-low k) dielectric material does protect the upper and low surf-aces of the layer of low k carbon-doped silicon oxide dielectric material while
Catabay Wilbur G.
Hsia Wei-Jen
Zhang Kai
Chaudhuri Olik
LSI Logic Corporation
Taylor John P.
Trinh (Vikki) Hoa B.
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