Composite layered chip package and method of manufacturing same

Details Composite layered chip package and method of manufacturing same Composite layered chip package and method of manufacturing same

2011-03-08

2011-03-08

Clark, S. V (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S724000, C438S107000

Reexamination Certificate

active

07902677

ABSTRACT:
A composite layered chip package includes a plurality of subpackages stacked. Each subpackage includes a main body, and wiring disposed on a side surface of the main body. The main body has a main part that includes at least one first-type layer portion. For any two vertically adjacent subpackages, the main body of the lower subpackage has a plurality of first terminals that are arranged on the top surface of the main part, while the main body of the upper subpackage has a plurality of second terminals that are arranged on the bottom surface of the main part. The main part of the main body of at least one of the plurality of subpackages includes at least one second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, while the second-type layer portion includes a defective semiconductor chip.

REFERENCES:
patent: 5571754 (1996-11-01), Bertin et al.
patent: 5953588 (1999-09-01), Camien et al.
patent: 7127807 (2006-10-01), Yamaguchi et al.
patent: 7652362 (2010-01-01), Jung et al.
patent: 2002/0096760 (2002-07-01), Simelgor et al.
patent: 2006/0001142 (2006-01-01), Jeung et al.
patent: 2007/0165461 (2007-07-01), Cornwell et al.
patent: 2009/0020889 (2009-01-01), Murayama et al.
patent: 2009/0045525 (2009-02-01), Matsushima et al.
patent: 2009/0085224 (2009-04-01), Choi et al.
patent: 2009/0321957 (2009-12-01), Sasaki et al.
patent: 2010/0140801 (2010-06-01), Anbai et al.
patent: 2010/0200959 (2010-08-01), Sasaki et al.
patent: 2010/0200998 (2010-08-01), Furuta et al.
patent: 2010/0207278 (2010-08-01), Kwon et al.
Gann, Keith D. Neo-Stacking Technology, HDI Magazine, 1999, (4 pages).

Affiliated with

Also associated with

Rating

Composite layered chip package and method of manufacturing same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Composite layered chip package and method of manufacturing same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Composite layered chip package and method of manufacturing same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2773168