Composite inverse T-gate metal oxide semiconductor device and me

Details Composite inverse T-gate metal oxide semiconductor device and me Composite inverse T-gate metal oxide semiconductor device and me

1990-12-19

1992-03-17

Prenty, Mark

357 239, 357 59, 357 231, H01L 2910, H01L 2906, H01L 2904, H01L 2701

Patent

active

050973010

ABSTRACT:
A high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation. An inverse T-gate comprising a polysilicon upper member and a tungsten lower member is formed on a p type substrate. A gate insulating layer is formed between the composite gate and the p type substrate. A pair of n- source/drain regions are formed apart in the p type substrate in alignment with the sides of the polysilicon upper member for forming a lightly doped drain region. An oxide sidewall spacer is formed adjacent to each side of the polysilicon upper member on the tungsten lower gate member for forming a mask for a n+ source/drain implant. The n+ source/drain implant is made in the n- source/drain regions in alignment with the oxide sidewall spacers for providing a source and a drain for the transistor. The tungsten lower gate member improves the transistors performance and makes the transistor viable for VLSI manufacturing techniques. The performance of the device can be further improved by placing silicide on the source gate, and drain regions. The reliability of the device can be further improved by grading the doping of the drain an additional time.

REFERENCES:
patent: 4907048 (1990-03-01), Huang
patent: 4949136 (1990-08-01), Jain
patent: 4978626 (1990-12-01), Poon et al.
patent: 4984042 (1991-01-01), Pfiester et al.
J. Sanchez, K. Hsueh & T. DeMassa, Drain-Engineered Hot-Electron-Resistant Device Structures: A Review, IEEE Transactions on Electron Devices, vol. 36, No. 6, (Jun. 1989) pp. 1125-1131.
J. R. Pfiester & F. K. Baker et al., A Self-Aligned LDD/Channel Implanted ITLDD Process With Selectively-Deposited Poly Gates For CMOS VLSI IEDM (Dec. 1989).
Tiao-yuan Huang & W. Yao et al., A Novel Submicron LDD Transistor With Inverse-T Gate Structure IEDM (Dec. 1986) pp. 742-745.
Ryuichi Izawa, Tokuo Kure, Shimpei Iijima and Eiji Takeda The Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI's IEDM (Dec. 1987) pp. 38-41.

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