Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2002-11-27
2004-06-08
Le, Dung A. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S660000, C257S634000, C257S635000, C438S791000
Reexamination Certificate
active
06747338
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
N/A
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor fabrication processes, and more specifically to a process of manufacturing semiconductor devices including Micro Electro-Mechanical Systems (MEMS) devices that include composite dielectric structures providing improved etch selectivity and reduced electrical leakage.
In recent years, MEMS devices have gained increased popularity in the field of microelectronics. For example, such MEMS devices may include micro-accelerometers, micro-mechanical filters, micro-resonators, micro-sensors, and micro-switches. A conventional process for manufacturing a MEMS device comprises providing a silicon substrate, forming a sacrificial oxide layer on a surface of the substrate, and patterning and etching the sacrificial oxide layer to define and expose a connection region for anchoring the MEMS device to the substrate surface. Next, a dielectric layer such as silicon nitride is deposited over the sacrificial oxide layer and the exposed anchor connection region. A polycrystalline silicon (“polysilicon”) layer is then deposited over the silicon nitride layer, and the sacrificial oxide layer is etched away to release at least a portion of the polysilicon layer and the adjacent silicon nitride layer. In the conventional MEMS fabrication process, the ratio of silicon to nitrogen in the silicon nitride layer is typically the stoichiometric ratio of three parts silicon to four parts nitrogen, i.e., Si
3
N
4
. Because Si
3
N
4
typically has very good electrical leakage characteristics, the sacrificial oxide layer can be etched and removed while assuring that the micro-structure remains electrically isolated from the silicon substrate.
One drawback of the conventional MEMS fabrication process described above is that stoichiometric silicon nitride is frequently incapable of satisfying the etch selectivity requirements for a given MEMS fabrication process. For example, MEMS structures frequently require extended etch times, e.g., up to 16 hours, in Hydrofluoric (HF) acid to release the micro-structure. However, stoichiometric silicon nitride typically has reduced etch selectivity to HF acid. As a result, during long release times, the HF acid can attack the Si
3
N
4
in the region where it is anchored to the substrate surface, thereby reducing the integrity of the anchor connection.
One way of improving the etch selectivity of stoichiometric silicon nitride to HF acid is to increase the thickness of the Si
3
N
4
layer. However, increasing the thickness of the stoichiometric silicon nitride layer can be problematic. For example, residual stresses in the thicker Si
3
N
4
layer can cause excessive wafer bow, micro-cracking and curling, and/or peeling from the underlying layers of the MEMS device.
In the above-described conventional MEMS fabrication process, a silicon nitride layer containing silicon in excess of the stoichiometric ratio may be employed instead of the standard stoichiometric silicon nitride. For example, such a silicon-rich nitride layer may be deposited using a Low Pressure Chemical Vapor Deposition (LPCVD) process. Because silicon-rich nitride typically has higher selectivity to oxide etch in HF acid, the sacrificial oxide layer can be etched and removed without appreciably affecting the silicon-rich nitride layer.
However, such use of silicon-rich nitride in the fabrication of MEMS devices also has drawbacks in that silicon-rich nitride frequently exhibits unacceptably high electrical leakage, especially when high voltages, i.e., greater than 40 V, are applied across the dielectric. For example, high voltage switching signals are often applied across dielectric layers included in micro-switch devices. In such devices, the electrical leakage that results from the application of high voltage switching signals (e.g., greater than 1 nA at 40 V) must typically be reduced or effectively eliminated to assure proper operation of the device.
Electrical isolation between the MEMS device and the silicon substrate can be improved by increasing the thickness of the silicon-rich nitride layer. However, even though there is typically less stress within a silicon-rich nitride layer than within an Si
3
N
4
layer, increasing the thickness of silicon-rich nitride layers can raise manufacturing costs by reducing throughput and exacerbating maintenance requirements of the MEMS device fabrication equipment.
It would therefore be desirable to have an improved process for manufacturing MEMS structures and devices. Such an improved MEMS device manufacturing process would allow the fabrication of dielectric structures that provide enhanced etch selectivity and reduced electrical leakage. It would also be desirable to have such a MEMS device fabrication process that has minimal impact on current fabrication equipment reliability and production processing.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a method of manufacturing semiconductor devices including Micro Electro-Mechanical Systems (MEMS) devices is provided that allows the fabrication of dielectric structures with improved etch selectivity, while maintaining minimal electrical leakage in the MEMS device. The dielectric structure fabricated by the presently disclosed method includes at least one silicon nitride layer that provides successively reduced silicon content from the sacrificial layer boundary toward the structural layer boundary of the MEMS structure.
In one embodiment, the method of manufacturing MEMS structures and devices includes providing a substrate, and forming a sacrificial layer on a surface of the substrate. Next, the sacrificial layer is patterned and etched to define and expose a connection region for anchoring the MEMS structure to the substrate surface. A dielectric layer is then formed over the sacrificial layer and the anchor connection region. Next, a structural layer is deposited over the dielectric layer. The sacrificial layer is then etched away to release at least a portion of the structural layer, which is anchored to the substrate surface at the connection region by the dielectric layer.
In the presently disclosed embodiment, the dielectric layer comprises a composite stack of discrete dielectric sub-layers. A first dielectric sub-layer comprising silicon-rich nitride is deposited over the sacrificial layer and the exposed anchor connection region, and at least one additional dielectric sub-layer having a reduced silicon content is formed over the silicon-rich nitride sub-layer. In a first embodiment, the additional dielectric sub-layer comprises a single stoichiometric silicon nitride sub-layer. In a second embodiment, at least two additional silicon nitride sub-layers are formed over the silicon-rich nitride sub-layer such that the silicon content of the nitride sub-layers is successively reduced from being in excess of the stoichiometric ratio, to being substantially equal to the stoichiometric ratio of standard silicon nitride.
In an alternative embodiment, the dielectric layer comprises a single dielectric layer deposited over the sacrificial layer and the exposed anchor connection region. The single dielectric layer comprises a silicon nitride layer providing a graded change in silicon content ranging from silicon-rich nitride near the sacrificial layer boundary, to stoichiometric silicon nitride near the structural layer boundary of the MEMS structure.
By fabricating a dielectric structure comprising silicon nitride having progressively reduced silicon content from the sacrificial layer boundary toward the structural layer boundary of the MEMS device, improved selectivity to the sacrificial layer etch can be achieved, while maintaining minimal electrical leakage in the device.
Other features, functions, and aspects of the invention will be evident from the Detailed Description of the Invention that follows.
REFERENCES:
patent: 5847454 (1998-12-01), Shaw et al.
patent: 6051511 (2000-04-01), T
Grosjean David E.
Nunan Thomas K.
O'Kane Denis M.
Sellars James S.
Analog Devices Inc.
Le Dung A.
Weingarten Schurgin, Gagnebin & Lebovici LLP
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