Composite dielectric layers

Details Composite dielectric layers Composite dielectric layers

2002-08-08

2004-01-06

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S506000, C257S501000, C257S041000, C438S348000, C438S361000, C438S207000, C438S427000

Reexamination Certificate

active

06674146

ABSTRACT:

BACKGROUND
1. Field
Integrated circuit processing and, more particularly, to the patterning of interconnections on an integrated circuit.
2. Background
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send or receive signals external to the chip. Popular types of interconnection include aluminum alloy interconnections and copper interconnections.
One process used to form interconnections, particularly copper interconnections, is a damascene process. In a damascene process, a trench is cut in a dielectric and filled with copper to form the interconnection. A via may be in the dielectric beneath the trench with a conductive material in the via to couple the interconnection to underlying integrated circuit devices or underlying interconnections. In one damascene process (a “dual damascene process”), the trench and via are each filled with copper material by, for example, a single deposition.
A photoresist is typically used over the dielectric to pattern a via or a trench or both in the dielectric for the interconnection. After patterning, the photoresist is removed. The photoresist is typically removed by an oxygen plasma (oxygen ashing). The oxygen used in the oxygen ashing can react with an underlying copper interconnection and oxidize the interconnection. Accordingly, damascene processes typically employ a barrier layer of silicon nitride Si
3
N
4
directly over the copper interconnection to protect the copper from oxidation during oxygen ashing in the formation of a subsequent level interconnection. In intelayer interconnection levels (e.g., beyond a first level over a device substrate), the barrier layer also protects against misguided or unlanded vias extending to an underlying dielectric layer or level.
In general, the Si
3
N
4
barrier layer is very thin, for example, roughly 10 percent of the thickness of the pre-metal dielectric (PMD) layer or interlayer dielectric (ILD) layer. A thin barrier layer is preferred primarily because Si
3
N
4
has a relatively high dielectric constant (k) on the order of 6-7. The dielectric constant of a dielectric material, such as an interlayer dielectric, generally describes the parasitic capacitance of the material. As the parasitic capacitance is reduced, the cross-talk (e.g., a characterization of the electric field between adjacent interconnections) is reduced, as is the resistance-capacitance (RC) time delay and power consumption. Thus, the effective dielectric constant (k
eff
) of a PMD layer or ILD layer is defined by the thin barrier layer and another dielectric material having a lower dielectric constant so that the effect of the high dielectric material typically used for the barrier layer (e.g., Si
3
N
4
) is minimized. Representative dielectric materials for use in combination with a barrier layer to form PMD or ILD layers include silicon dioxide (SiO
2
), fluorinated silicate glass (FSG), and carbon-doped oxide (CDO).
As technologies advance, the distance (e.g., pitch) between interconnections decreases as more devices and more interconnections (e.g., interconnect lines) are formed on a structure. Thus, the effective dielectric constant (k
eff
) of a PMD or ILD layer is significant.


REFERENCES:
patent: 5081053 (1992-01-01), Heremans et al.

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