Composite code match filters

Details Composite code match filters Composite code match filters

1999-09-30

2002-05-07

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S149000, C375S367000

Reexamination Certificate

active

06385259

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to a telecommunication apparatus and, more particularly, to chip and frame synchronization stages of a mobile terminal, such as a cellular phone.
Telecommunications establish communications, usually between widely separated points, by electrical or electronic means, with one such electronic means being a mobile terminal, such as a cellular phone. Mobile terminals have an acquisition mode that gathers data by locking into a signal containing data representative carrying a code. Mobile terminals communicate with the home or base station using data formats and protocols based on industry standards, such as the Third Generation Partnership Project (3GPP) known in the art and is described in the Technical Specification V1.0.1 (1999-03).
The acquisition mode of the mobile terminal for the 3GPP standard can be achieved by a three stage electronic device, with the first stage being a receiver stage and performing a chip synchronization function, the second stage performing a frame synchronization function, and the third stage performing a scrambling code identification function. The given description herein refers to various terms associated with the 3GPP standard whose complete definition is more fully described in the 3GPP standard. The 3GPP standard has predetermined data format with a first search code (or primary synchronization code) thereof being herein termed as a Golay code, which can be constructed hierarchically by two codes. To easier describe the formation of Golay code, we define subcode, composite code, which can be described as follows:
Golay code=Z, Z, Z, /Z, /Z, Z, /Z, /Z, Z, Z, Z, /Z, Z, /Z, Z, Z
where /Z=complement of Z;
subcode=Z=0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0;
and
composite code=1, 1, 1, −1, −1, 1, −1, −1, 1, 1, 1, −1, 1,
which corresponds to the polarity of the subcode in Golay code.
The Golay code that 3GPP is using has 256 coefficient [C
0
C
1
. . . C
255
]. In the implementation of the present invention, and in a manner known in the art, binary signal “0” is mapped (modulated) to “1” and binary signal “1” is mapped to “−1”. Further, the present invention is primarily concerned with the chip and frame synchronization stages of the mobile terminal and the benefits of the present invention may be better understood with reference to a prior art receiver stage which performs chip synchronization and that may be further described with reference to FIG.
1
.
FIG. 1
illustrates a code match filter
10
comprised of a shift register
12
having a plurality, n, of delay lines
12
A serving as stages thereof and each consisting of a tap-delay, a plurality, n, of multipliers
14
and a plurality, n, of adders
16
. The multipliers
14
and adders
16
are arranged as shown so as to sequentially multiply and add together outputs of the stages of the shift register
12
in a cumulative manner. The code match filter
10
receives a signal containing incoming data
18
by way of signal path
18
A. As will be further described, the incoming data is actually two separately handled data quantities, that is, I channel data and Q channel data each being separately processed by a code match filter
10
. The code match filter
10
operates to places its output on signal path
20
. As to be more fully described hereinafter with regard to the present invention, the incoming data
18
is filtered against a first search code (or primary synchronization code) residing in and fetched from a memory block
22
A, such as a RAM, to derive slot boundaries in the processor
22
.
Although the structure of
FIG. 1
has the advantage of fast acquisition, it also has the disadvantage of being of a relatively large chip size. Also, since each delay element is typically a set of D-flip flops (the number of D-flip flops depends on the number of bits the input carries) operating at 7.68 MHz (2 times the chip rate 3.84 MHZ, as defined in 3GPP), the code match filter
10
may require two clock drivers
24
each having an output path
24
A to drive the 256 delay elements in serial. It is desired that a chip synchronization composite code match filter be provided that performs the same function as the code match filter
10
, but reduces the required number of delay elements and reduces the number of clock drivers. It is further desired to utilize the principles of the chip synchronization composite code match filter of the first stage of the mobile terminal to provide a frame synchronization composite code match filter for the second stage of the mobile terminal.
SUMMARY OF THE INVENTION
The invention in one aspect is a receiver stage of a mobile terminal, such as a cellular phone and in another aspect is a frame synchronization stage of the mobile terminal.
The embodiments of the invention receive data carrying a search code which is hierarchically composed of two codes. The data is filtered against one of the two codes and placed in a temporary buffer. The other code is periodically accessed so as to be multiplied with and then added to the contents of the temporary buffer to determine the correlation between the contents, of the two codes which, in turn, determines and detects the search code being carried by the data.
The receiver stage of the mobile terminal may primarily take the form of a chip synchronization composite code match filter, wherein the term “chip” is known in the art. The chip synchronization composite code match filter despreads the incoming signal with a primary synchronization code. The chip synchronization composite code match filter comprises a demultiplexer, first and second subcode match filters, first and second buffers, a circular buffer, a control unit, a multiply and accumulation unit, and a multiplexer. The demultiplexer receives the signal containing data and split the signal into first and second output signals representative of an on-time and a half-chip delay signal, respectively. The first and second subcode match filters respectively receive the first and second output signals of the demultiplexer with a set of the coefficients. The first and second buffers, respectively, temporarily store the output signals of the first and second subcode match filters. The circular buffer internally circulates a composite code. The control unit accesses and makes available the contents of each of the first and second buffers and that of the circular buffer. The multiply and accumulation unit then multiply the subcode correlation output, which is stored in the first and second buffer with the composite code which stored in the circular buffer and accumulated therein. The multiply and accumulation unit determines the correlation of the input data and Golay code with respect to different chip offsets. The multiplexer multiplexes the two (2) output correlation streams into one output stream.
The frame synchronization composite code match filter incorporates the operating principles of the chip synchronization composite code match filter but needs only comprising one subcode match filter, a shift register, a holding register, a correlator, a lookup table and four buffers.
The invention also provides a method that is applicable to both the chip and frame synchronization operations. The method takes advantage of the hierarchical Golay code being used by the incoming signal. The Golay code as described earlier, can be constructed hierarchically by two codes. More particularly, the present invention defines one of them the subcode and the other the composite code. The subcode is comprised of a predetermined number of coefficients and the composite code is comprised of a predetermined number of coefficients. The method further includes providing at least one shift register having a predetermined number of sequential stages corresponding to the predetermined number of coefficients of the subcode. The shift register has an input stage connected to receive the signal and an output stage.
The method further provides a plurality of multipliers and adders arranged

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