Composite alignment mark scheme for multi-layers in lithography

Details Composite alignment mark scheme for multi-layers in lithography Composite alignment mark scheme for multi-layers in lithography

2007-05-22

2007-05-22

Dang, Phuc T. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C438S462000, C365S150000

Reexamination Certificate

active

11074602

ABSTRACT:
Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.

REFERENCES:
patent: 6416912 (2002-07-01), Kobayashi et al.

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