Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1999-08-25
2003-03-04
Martin, David (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S803000, C361S735000, C361S736000, C361S760000, C361S761000, C361S763000, C361S764000, C361S782000, C361S811000, C361S785000
Reexamination Certificate
active
06529385
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is related to integrated circuit interconnection, and more particularly to an array of components for connecting integrated circuits to other devices.
BACKGROUND OF THE INVENTION
In today's world of high technology, demand for increased computing power is on the rise. Applications continue to increase in complexity and each increase in speed and efficiency to meet the new complexities is followed by a new demand for more capability. In this quickly advancing process, the density and speed of signals used on integrated circuits has escalated. Nowhere is this more apparent than in microprocessor and memory data buses. The increased density and speed has made testing of, and interconnection to, new technologies more difficult with each step because of difficulties in connecting testing or other devices to the high density signals without adversely affecting the test results or integrated circuit performance.
One solution used is to take a typical processor socket, lift it up, and put an interposer between the socket and the signals. The signals then need to be routed out to a buffer or attenuator before being connected to a probe for testing or to another device. The routing of the signals out to the buffer or attenuator adds interconnect distance to the signals and thereby significantly decreases signal performance which limits the effectiveness of testing or other interconnection activities.
Another solution is to connect the testing or other devices into extra connectors attached to the signals. This used to be an adequate solution when signal and bus speeds were 100 MHz or less. However, with bus and signal speeds surpassing 400 MHz, this is no longer a feasible solution without undesirable impact on the signals. This impact will have the same effect as the routing length problems above and severely limit the effectiveness of the desired testing and integrated circuit performance.
It is possible to mount resistors flat onto the circuit board to act as the first stage (series resistor) of a probe attenuator/isolator for each signal that limits the effect on the bus or signal. This process can be difficult in high density signal areas because of the lack of space for mounting the resistors, or the need to use extremely small resistors for which there is currently no qualified circuit board mounting process. Additionally, this solution still requires the signals to be routed out from high density areas. The routing adds significant interconnect lengths before reaching the probe and the associated vias reduce the effectiveness of the power and ground planes. The added interconnect length introduces parasitics that degrade testing accuracy and integrated circuit capabilities and limits the effectiveness of the solution.
Another solution to the signal degradation problem is to use ohmic printed circuit board layers. While this method may not degrade the signals and eliminates the problem of fitting resistors onto the circuit board, there are new problems. Ohmic layers have increased variations in resistor tolerance which sacrifices isolation and performance. Additionally, there remains the, need to route the isolated signals out to a probe connection that introduces long interconnect lengths and the associated degradation in testing or integrated circuit performance from parasitics. Finally, ohmic layers are expensive making them generally undesirable.
Thus, what is needed in the art is an apparatus and method for low cost, minimally invasive connectivity to high speed and high density electrical signals that can also facilitate accurate test results.
SUMMARY OF THE INVENTION
One embodiment includes an interconnect device having an insulating substrate having first and second sides and a plurality of sites. Each site includes a first node on the first side, a second node on the second side and at least one component connected between the first and second nodes. The components include active or passive components. Each component is substantially normal to the first and second sides of the insulating substrate.
Another embodiment includes a method for testing an integrated circuit. The method includes connecting at least one test probe to an adapter. The adapter includes an insulating substrate having first and second sides and a plurality of sites. Each site includes a first node on the first side, a second node on the second side and at least one component connected between the first and second nodes. The components include active or passive components. Each component is substantially normal to the first and second sides of the insulating substrate. Each site further includes a first electrical connector connected to the second node. The method further includes connecting the adapter to the integrated circuit using the first electrical connectors of the plurality of sites and testing the integrated circuit using a test unit attached to each of the test probes.
A further embodiment includes an interconnect device. The interconnect device includes an insulating substrate having first and second substantially parallel, planar surfaces. The insulating substrate further has a plurality of holes passing through the insulating substrate such that a center line of each of the plurality of holes is substantially normal to the first and second planar surfaces. A plurality of surface mount electrical components, having a body with first and second conductive interconnects located at distal ends of the body, are located in the plurality of holes such that the first conductive interconnect of each of the plurality of surface mount electrical components is located proximate to, the first planar surface and the second conductive interconnect of each of the plurality of surface mount electrical components is located proximate to the second planar surface.
The invention further includes other apparatus and methods of varying scope.
REFERENCES:
patent: 5057041 (1991-10-01), Yu et al.
patent: 5213522 (1993-05-01), Kojima
patent: 5624277 (1997-04-01), Ward
patent: 5761036 (1998-06-01), Hopfer et al.
patent: 6142831 (2000-11-01), Ashman et al.
Brady Gary W.
Hampton, III Harry L.
Kabadi Ashok N.
White Michael T.
Intel Corporation
Martin David
Schwegman Lundberg Woessner & Kluth P.A.
Tran Thanh Y.
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