Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1998-04-28
2001-02-20
Gaffin, Jeffrey (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S768000, C361S783000, C257S723000, C257S737000, C257S738000, C257S778000, C174S256000, C174S258000, C174S260000, C438S108000, C438S126000
Reexamination Certificate
active
06191952
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to electronic packaging and more particularly to methods and apparatus for improving the reliability of flip-chip connections by accommodating for differences in thermal expansion of the chip and the substrate to which it is attached.
BACKGROUND
Integrated circuit (IC) chips or modules are often connected to chip carriers, and sometimes directly to PC boards or cards, by what is commonly referred to as C4 (controlled-collapsed-chip-connection) or flip-chip attachment technology. Small solder bumps or balls are formed on an active surface of the chip. The chip is then turned over (hence the name “flip-chip”) and placed on the carrier, board or other substrate to which it will be attached. The components are heated to cause the solder to reflow in a controlled collapse which completes electrical connections between the chip and substrate. This technology has numerous advantages, including compact connections, electrical performance and cost, that have made it one of the industry standards. There are certain disadvantages, however, that have prevented even wider adoption.
One of the more significant disadvantages results from differences in the coefficients of thermal expansion (CTE) of the chip and substrate. Common chip materials such as silicon, germanium and gallium arsenide usually have CTEs of about 3 to about 6 ppm/° C. Organic chip carriers to which the chips are attached and organic printed circuit boards and cards, which are usually composites of organic dielectrics and metallic circuitry, tend to have CTEs between about 12 and about 20 ppm/° C. As these components are heated and cooled the substrates expand and contract much more than the chips. With a simple chip to substrate connection, the strain from the unequal expansion is absorbed primarily by the soft solder. With repetitive thermal cycles, which are inescapable with many electronic components, the solder joints are likely to fail.
A conventional approach to this problem is to surround the solder joints with a dielectric underfill material that matches or approximates the CTE of the solder joints, which is typically about 22 to about 28 ppm/° C. Typical underfill materials are epoxy-based anhydride systems. They are normally heavily filled with very small particles of materials such as silicon dioxide to produce the desired CTE. The filler also gives the underfill a high modulus (as used herein, the term “modulus” refers to the storage modulus) typically greater than about 2 GPa or about 300 ksi. The underfill bears most of the load resulting from the differential expansion of the chip and substrate, and reduces the strain on the solder joints. However, by restricting the differential expansion between the chip and substrate, the relatively strong coupling between the chip and carrier has a tendency to warp both the chip and carrier. This increases loads acting normal to the surface of the substrate to which to which the carrier is attached. For example, as the package cools after the carrier has been attached to a printed circuit board or card, typically with an array of solder balls on BGA, the chip and carrier have a tendency to bow upward in the middle, which generates a tensile load on the balls at the center of the array between the carrier and the board or card. This can lead to premature failure of the BGA.
There have been many attempts to mitigate these problems, including stiffeners with a desirable CTE and layers of compliant material within a multi-layer organic printed circuit board or card. Stiffeners are expensive, however, and compliant layers within a board introduce stress concentrations where plated through holes (PTHs) pass through them became of the shear deformation. Thus, the need for reliable and inexpensive ways to accommodate for differential thermal expansion between chips and circuitized organic substrate such as chip carriers and printed circuit boards remains.
SUMMARY OF THE INVENTION
The packages and methods of this invention accommodate CTE differentials between chips and the organic dielectric carriers, boards or other substrates to which the chips are attached with a layer of compliant material positioned between the chip and substrate. The solder connections between the chip and substrate extend through this compliant layer, which is normally used with a conventional underfill. The compliant layer is positioned between the underfill and substrate, and should have a modulus of less than about one-half the modulus of the underfill. Compliant materials with a modulus of less than about 100,000 psi are normally desirable, and materials with a modulus between about 20,000 and about 50,000 psi are preferred.
During thermal cycling of the chip and substrate, one side of the compliant layer conforms to the movement of the underfill and other side of the layer conforms to the movement of the substrate. In doing so, the compliant layer reduces coupling between the chip and substrate, thereby reducing their bending. Various compliant dielectrics can be used for the compliant layer, including rubbery materials such as silicone and visco-plastic polymers such as polytretaflouroethylene. Photosensitive interpenetrating polymer networks, such as those used as masks for the completion of solder connections, are preferred.
Other advantages of this invention will be apparent from the following description.
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IBM Technical Disclosure Bulletin, “Elastic Thermal Compensation of Chip Carriers”, v.40, No. 4, pp. 85-86 (Disclosure Text including indication of Apr. 1, 1997 publishing date).
U.S. application No. 09/080,117, Caletka et al., filed May 15, 1998; for Thermally Enhanced and Mechanically Balanced Flip Chip Package and Method of Forming.
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Jimarez Miquel A.
Johnson Eric A.
Li Li
Obrzut Jan
Driggs Lucas Brubaker & Hogg Co. L.P.A.
Gaffin Jeffrey
International Business Machines - Corporation
Lucas James A.
Vigushin John B.
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