Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-01-25
2002-10-22
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S125000, C438S107000, C438S118000, C438S127000, C438S119000
Reexamination Certificate
active
06468830
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor chip mounting and connection, and more particularly, relates to semiconductor chip packages including flexible leads having enhanced fatigue-resistant and to assembly methods therefor.
BACKGROUND OF THE INVENTION
Semiconductor chips are connected to external circuitry through electrical contacts on a front face of the chip. Each contact on the chip must be connected to external circuitry, such as the circuitry of a supporting substrate or circuit panel. Various processes for making these interconnections use prefabricated arrays of leads or discrete wires. For example, in the so-called tape automated bonding or “TAB” process, a dielectric supporting tape, such as a thin foil of polyimide includes an array of metallic leads on one surface of the dielectric film. These leads are aligned with the contacts on the front face of the chip. The dielectric film is juxtaposed with the chip so that the leads extend over the front or contact bearing surface on the chip. The leads are then bonded to the contacts of the chip, as by ultrasonic or thermocompression bonding. The terminals on the dielectric film may then be connected to external circuitry for electrically interconnecting the chip and the external circuitry.
The rapid evolution of the semiconductor art in recent years has created a continued demand for semiconductor chip packages having progressively greater numbers of contacts and leads in a given amount of space. An individual chip may require hundreds or even thousands of contacts, all within the area of the front face of the chip. Certain complex semiconductor chips currently being used have contacts spaced apart from one another at center-to-center distances of 0.1 mm or less and, in some cases, 0.05 mm or less. With such closelyspaced contacts the leads connected to the chip contacts must be extremely fine structures, typically having a smaller bonded surface than the contacts onto which they are bonded so that the adjacent leads do not electrically short. Such fine structures are susceptible to damage and deformation.
U.S. Pat. No. 5,489,749, the disclosure of which is incorporated by reference herein, describes an improved system for connecting semiconductor chips to external circuitry. Certain disclosed embodiments of the invention utilize a connection component including a flexible dielectric sheet and electrically conductive leads. Each lead has a connection section extending across a gap in the dielectric sheet. The connection sections of the leads are flexible. Preferably, one end of each lead, sometimes referred to as the tip end, is detachably secured to the dielectric sheet, whereas the other end is permanently secured to the dielectric sheet and connected to a terminal mounted on the dielectric sheet. The connection sections of the leads are bonded to the contacts on the chip by engaging each connection section with a tool, forcing the tool downwardly to break the tip end of the lead from the dielectric sheet and bringing the connection section into engagement with a contact on the chip.
Leads are typically bonded to contacts on a semiconductor chip or other microelectronic element using ultrasonic, thermocompression or thermosonic bonding. In the bonding process, the bonding region of each lead is engaged by a bonding tool which bears on the top surface of the lead in the bonding region and forces the lead downwardly into engagement with the contact. Energy supplied through the bonding tool causes the bonding metal to join with the contact. Typically, the leads are bonded to the chip contacts with the bonding tool using heat, force, ultrasonic energy, or a combination of two or more thereof, for a given time period. If incorrect force, heat and/or ultrasonic energy is used, the bond between the leads and the contacts may be too weak to withstand thermal cycling stresses during operation of the chip (heating and cooling cycles during operation). Also, the bonding tool may create areas of the lead which are prone to early fatigue during thermal cycling because of excessive non-uniform deformations in the bonding region typically causing early breaks in the lead at the point the lead bends up from the chip surface (commonly referred to as a “heel break”).
Copending U.S. patent application Ser. No. 09/179,273 filed Oct. 27, 1998 is incorporated by reference herein. In certain structures taught in said copending application, a connection component includes flexible leads incorporating a structural material such as copper, gold, alloys of these metals or other metals. Each lead is provided with a thin layer of a fatigue-resistant alloy, such as the alloys commonly referred to as shape memory alloys. The fatigue resistant alloy preferably is provided on the bonding or bottom side of the lead which is bonded to a contact during use of the component. A layer of a readily bondable material such as gold, palladium or other metal compatible with the contact to which the lead is to be bonded is applied on the bottom or bond side of the lead covering the fatigue-resistant alloy at least in the area of the lead which will engage the contact during use.
Akagawa, U.S. Pat. No. 5,677,576 discloses a semiconductor package including a semiconductor chip having one surface provided with an insulating passivation film having openings exposing aluminum contact pads formed on the surface of the semiconductor chip in a predetermined pattern. An anisotropic conductive sheet is formed over the passivation film and the contact pads. The anisotropic conductive sheet is formed of a resin containing conductive fillers such as metallic powders whereby the application of pressure to the film results in electrical conductivity in the pressed direction due to the continuity of the conductive fillers caused by the pressure. The metallic powders may be, for example, metallic particles in the nature of resin particles coated with nickel plated layers or the like or metallic particles such as of gold, nickel or the like.
Electrical conductive circuit patterns are formed in a predetermined arrangement on the exposed surface of the anisotropic conductive sheet. The circuit patterns are formed by adhering a metallic foil, such as a copper foil to the anisotropic conductive sheet and etching the foil in conformity with the predetermined circuit patterns. A photoresist film is deposited over the anisotropic conductive sheet and the circuit patterns. The photoresist film is provided with openings in the nature of via holes for receiving conductive bumps to provide external termination to the circuit patterns. By compressing the anisotropic conductive sheet in the region overlying the contact pads, electrical continuity to the circuit patterns is provided.
Tang, et al., U.S. Pat. No. 5,749,997 discloses another semiconductor device using an anisotropic conductive sheet. The device includes a semiconductor chip supporting on its major surface a plurality of composite bumps. The bumps are formed of a polymer body such as polyamic acid polyimide covered by a conductive metal coating such as a composite of chrome/gold or nickel/gold. An anisotropic conductive sheet is compressed over the composite bumps and the surface of the semiconductor chip. A dielectric layer having leads formed thereon such as in the conventional TAB or tape automated bonding process is arranged overlying the surface of the anisotropic conductive sheet. The leads may be fully supported by the dielectric sheet, or have portions extending within a window formed within the sheet. In either event, the dielectric sheet is arranged with the leads having one end overlying each of the composite bumps. Upon compression of the anisotropic conductive sheet, the conductive particles therein will make electrical contact with the leads and the conductive metal coating on the composite bumps.
Chillara, U.S. Pat. No. 5,627,405 discloses an anisotropic conductive sheet adhered to the surface of an integrated circuit semiconductor chip which includes a plurality of input/o
Graybill David E.
Lerner David Littenberg Krumholz & Mentlik LLP
Mitchell James
Tessera Inc.
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