Compliant leads for area array surface mounted components

Details Compliant leads for area array surface mounted components Compliant leads for area array surface mounted components

1999-11-05

2002-01-15

Sircus, Brian (Department: 2839)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S777000

Reexamination Certificate

active

06339534

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to interconnection elements for interconnecting integrated circuit packages to printed circuit boards in surface mounted area array assemblies, using flat connection elements of particular configurations and arrangements.
BACKGROUND OF THE INVENTION
In the field of integrated circuit packages, area array integrated circuit packages are becoming more and more frequently used. Area array packages include ball grid arrays and column grid arrays. The main advantage of the area array products is the large number of I/O contacts which are provided as the complete bottom surface of the module or package is used, in comparison with the peripheral lead products, which make use of only contact locations adjacent to the periphery of the package. These products are attached to printed circuit boards using established surface mount techniques. Area array packages include packages with either fully or partly populated bottom surfaces.
In preparation for surface mounting on a printed circuit board for example, solder balls or solder columns are permanently attached to the IC package, which in turn are permanently attached to the printed circuit board pads by soldering. The assembled structure includes interconnect elements, for example solder balls, with two solder joints, one to a contact on the package surface, one to a contact on the printed circuit board surface.
One major restriction of the area array interconnection technology is the reliability of the solder joints. An assembled product is subjected to thermal variations with significant stresses resulting in the solder joints because of the difference in thermal expansion between the printed circuit board and the IC package. This results from the differences in the coefficient of thermal expansion of the elements involved. Different factors, including operating temperature of the assembled product, compliance of the interconnection elements, number of thermal cycles, size of the package, package material, have an impact on the amount of resulting stress on the solder joints. Improvements in reliability are needed for the more extreme conditions and critical factors.
One method to reduce stress in the solder joints is to increase the compliance of the interconnection element. For example, instead of using a solder ball, a well-known solution is to use a solder column interconnecting element. Assembled solder ball connections provide short cylindrical interconnections, compared to solder columns which provide much longer cylindrical connections, typically in the order of three times longer. Longer cylindrical connections are more compliant, so lower stress is transmitted to the solder joint.
There are important drawbacks with the use of solder column interconnections. With longer connection elements, the resulting product is more susceptible to damage resulting from handling. Longer elements result in an increase of the self-inductance of the connections, which is detrimental to the electrical performance of the IC package. It would be preferable to use a connection element that is more compliant than solder ball but with a length equivalent to a solder ball.
Flat leads can be more compliant than cylindrical connections such as balls or columns. In the past, flat leads have been used extensively as interconnection elements in peripherally connected products such as quad flat packs. U.S. Pat. No. 5,647,124 which issued Jul. 15, 1997 to Chan et al entitled “Method of Attachment of a Semiconductor Slotted Lead to a Substrate”; U.S. Pat. No. 4,647,126 which issued Mar. 3, 1987 to Sobota entitled “Compliant Lead Clip”; and U.S. Pat. No. 5,317,479 which issued May 31, 1994 to Pai et al, entitled “Plated Compliant Lead”, provide examples of the use of flat leads in peripheral connection packages. For today's high density IC packages, peripheral connection packages are not practical because they do not offer a sufficient number of I/O connections, because of the inherent configuration where only the outside peripheral area of the packages is used to connect to the printed circuit card.
In the patent literature, there have been some descriptions of the possible use of flat leads in area array packages. U.S. Pat. No. 4,751,199 which issued Jun. 14, 1999 to Phy, entitled “Process of Forming a Compliant Lead Frame for Array-Type Semiconductor Packages” teaches the use of flat leads on an area array IC package. A drawback with this disclosed approach is that all leads are aligned in the same direction. In actual conditions stresses result in directions extending radially outward from the center of the module. Disposition of the leads on the package must be optimized in order to get low stress on the joints and appropriate reliability with a flat lead arrangement on an area array package. These are some of the shortcomings of this reference subsequently addressed by the subject invention.
U.S. Pat. No. 5,420,461 which issued May 30, 1995 to Mallik et Al., entitled “Integrated Circuit Having a Two-Dimensional Lead Grid Array” shows a configuration very similar to what is disclosed in Phy, and suffers from the same drawbacks. The leads are all aligned in the same orientation, which has been found to be not optimal.
Also of interest are the teachings of U.S. Pat. No. 5,490,040 which issued Feb. 6, 1996 to Gaudenzi et al and entitled “Surface Mount Chip Package Having an Array of Solder Ball Contacts Arranged in a Circle and Conductive Pin Contacts Arranged Outside the Circular Array”. The point of neutral stress of an array is discussed and the recognition that the degree of stress in the leads and contacts in a circuit package radiate from this neutral point. Thus it is proposed in this reference that ball contacts should only be used up to a certain radial distance from the neutral point, and further out, pin connections should be used in order so that the effects of stress can be minimized.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide an area-array integrated circuit package with increased reliability in the interconnections in the presence of thermal stress.
It is a further object of this invention to provide a new, practical and more reliable compliant interconnection element for interconnecting electronic circuit components.
It is another object of this invention to provide flat, compliant, connecting elements, or leads, which are oriented in an IC package such that each flat lead faces the neutral point of the package. The flat connection elements are aligned in the orientation of optimal compliance and flexibility, thereby offering compliance to thermal variation that is superior to that of commonly used solder balls or columns.
It is another object of the present invention to provide interconnections from one planar substrate to another, where the substrates may be printed circuit boards, ceramic cards, or other substrates common in the field.
According to one aspect of the invention there is provided an integrated circuit package having an array of contacts on a surface of the package and said array of contacts has a neutral point. A plurality of compliant leads is provided such that each lead is connected to one of said contacts on the surface of the package. Each lead extends outwardly from a respective contact on said surface and has a generally rectangular cross-section shape such that each lead has a width dimension and a thickness dimension wherein the width dimension is greater than the thickness dimension. At least some of the leads are arranged and oriented around the neutral point of said array such that the width dimension of said at least some of the leads face the neutral point.
According to another aspect of the invention, there is provided an electronic circuit assembly comprising a first planar component having an array of contacts on one surface such that said array of contacts has a neutral point and a second planar component having array of contacts on one surface thereof such that said array of contacts on the surface of t

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