Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-10-04
2002-07-02
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000, C439S065000, C029S843000
Reexamination Certificate
active
06414248
ABSTRACT:
BACKGROUND
This invention relates to techniques for forming a compliant interfacial mechanical, thermal and/or electrical bond interface between planar surfaces.
A single chip module (SCM) or multichip module (MCM) for military or space applications typically has a surface mount ceramic single chip package (SCP) or multichip package (MCP) for hermeticity, reliability, thermal and double-side printed wiring board assembly (PWA) requirements.
A peripheral leaded ceramic quad flat pack (CQFP) package with a high pin count requires a large ceramic body and an even larger PWB footprint. Even with a small lead pitch of 20 mils, a square CQFRP package with 144 to 576 pins requires a ceramic body size of about 0.80 to 2.96 inches on a side, a PWB footprint size of about 1.16 to 3.32 inches on a side (about 0.36 inches larger than the ceramic body on each side due to formed peripheral leads) and has a surface interconnect density (number of PWB contacts divided by the PWB footprint area) of 107 to 52 contacts per square inch. In contrast, a square ceramic area array (CAA) package with 144 (12×12) to 576 (24×24) pins, such as a land grid array (LGA), ball grid array (BGA), column grid array (CGA) or pin grid array (PGA), with a 50 mil grid pitch requires a ceramic body and PWB footprint size of 0.60 to 1.20 inches on a side with a constant interconnect density of 400 p ins per square inch.
In comparis on, these CAA packages require only 0.27 to 0.13 times the area and offer 3.74 to 7.65 times the interconnect densities of their equivalent CQFP packages. The PWB footprint area and interconnect density advantages of CAA over CQFP packages increases with pin count.
Surface mount attachment of large heavy ceramic packages to a PWB for military and space applications presents several challenges in terms of electrical and thermal erformance, mechanical integrity, reliability, assembly and rework. For one, the temperature coefficient of expansion (TCE) differences between the package body and PWB materials, along with PWB deflections, under worst case shock, vibration, acceleration and temperature cycling environments can cause distortions and high stress levels in the attachment and interconnect interfaces.
The attachment and interconnect interfaces of a surface-mounted CQFP package are typically separate. The attachment interface is comprised of interfacial solder and/or epoxy between the ceramic body and the PWB. The interconnect interface is comprised of relatively long gull-lead-formed peripheral leads which provide X-axis, Y-axis and Z-axis compliance.
The attachment and interconnect interfaces of CAA packages (LGA, BGA, CGA or PGA) are one and the same. With conventional vapor phase solder surface-mount assembly, the attachment/interconnect interface is comprised of an interfacial array of short direct vertical solder ball, solder column or pin connections. This array of rigid vertical interfacial connections has some X-axis and Y-axis compliance (amount dependent upon connection aspect ratio or length divided by cross-sectional area), but offers little or no Z-axis compliance. For an area array package to be used in military and space applications, its interfacial attachment/interconnect interface should be modified to provide enough X-axis, Y-axis and Z-axis compliance to absorb distortions of the interfacial interface between the package and the PWB and to reduce stress on solder (or other adhesive) joints that leads to attachment and/or connection failures.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved method of interfacially mechanically bonding two surfaces with one or more compliant paths that may also be electrically and/or thermally conductive, such as mounting and interconnecting an electronic device to a PWB.
According to the invention, a compliant (flexible) interposer is used to form part of one or more interfacial electrical, mechanical and/or thermal attachment/conduction paths between two surfaces, such as a PWB and a SCM or MCM (LGA, BGA, CGA or PGA), a connector, a heat sink or another PWB. Assuming that the surfaces to be connected and the interposer lie parallel to a horizontal X-Y plane, each electrical, mechanical and/or thermal path between the two interposer surfaces is made through a path comprised of two vertical columns (attachment interfaces) of adhesive material (one between each surface and the interposer) and a horizontal and possibly a vertical path through the interposer itself. Each path through the interposer is comprised of a pair of attach pads, one on each side and displaced from each other in the X and Y directions, at least one surface or buried trace to provide a horizontal connection and one or more vias to provide a vertical connections if the attach pads are not on opposite sides of the same conductor layer.
The example depicts the case of the horizontal path comprised of two opposing surface traces with vias connecting them. Each surface trace has an integral (mask-defined) attachment pad at one end and an integral via pad at the opposite end. Each via connects the attach pad portion of one surface trace to the via pad portion of the opposing surface trace. Therefore, each mask defined attach pad has redundant trace-via and via-trace conduction paths to its mating mask-defined (X,Y displaced) attach pad on the opposite side of the interposer.
According to one aspect of the invention, conductive or non-conductive bumps (e.g. solder, epoxy or thermoplastic) are first applied to one or more pairs of the attach pads on opposite sides of the interposer and are subsequently bonded to mating attach pads on a PWB and a device to form one or more electrical, mechanical and/or thermal connection paths between the PWB and device.
According to one aspect of the invention, the surface trace width is tapered from the full diameter of the integral attach pad at one end to the full diameter of the integral via pad at the other end to minimize electrical and thermal resistance between attach pad pairs.
A feature of the present invention, it is especially useful in improving the reliability of interfacial interfaces under high G-force applications, such as space craft and high performance aircraft.
Other objects, benefits and features of the invention will apparent to one of ordinary skill in the art from the drawing and following description.
REFERENCES:
patent: 3546775 (1970-12-01), Lalmond et al.
patent: 3571923 (1971-03-01), Shaheen et al.
patent: 5381306 (1995-01-01), Schumacher et al.
patent: 6201194 (2001-03-01), Lauffer et al.
Cuneo Kamand
Greenstien Robert E.
Honeywell International , Inc.
Norris Jeremy
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