Complex type correlator in CDMA system and initial...

Details Complex type correlator in CDMA system and initial... Complex type correlator in CDMA system and initial...

2000-02-14

2003-11-18

Pham, Chi (Department: 2631)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S343000, C370S512000

Reexamination Certificate

active

06650693

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a correlator for acquiring initial synchronization and initial synchronization acquiring method using the same from signals to be inputted to receiving stages of a base station and a mobile station in a Code Division Multiple Access (CDMA) system, and more particularly to a complex type correlator in the CDMA system and initial synchronization acquiring method using the same which uses an active type correlator together with a passive type correlator.
BACKGROUND OF THE INVENTION
Generally, a pilot channel may be interchanged between receiving stages of a base station and a mobile station in the CDMA system to lock initial synchronization. At this time, a spread signal may be loaded on the pilot channel, the spread signal being composed of 64 chips or 128 chips per one bit. Also, the spread signal is logically multiplied by a pseudo random code, then the multiplexed result is added over a predetermined times, in which the initial synchronization may be acquired from a maximum added value by means of a correlator.
The correlator may be classified into an active correlator and a passive correlator.
There is shown in
FIG. 1
the active correlator, in which a spread signal r
k
at a receiving stage of a base station or a mobile station is inputted into a multiplier
10
by one chip, then the inputted spread signal is logically multiplied in recursive pattern with a pseudo random code c
k
stored in the multiplier
10
over a predetermined times. The multiplied result is added accumulatively over a predetermined times by means of an accumulator
20
, in which initial synchronization may be acquired from a maximum added value out of the accumulated values d
k
.
Further, referring now to the operation of the passive correlator shown in
FIG. 2
, all the chips of received spread signal r
k
are shifted in turn in a plurality of shift registers
40
#
1
-
40
#n, which respectively output the shifted chips of the spread signal r
k
into a plurality of multipliers
30
#
1
-
30
#n, which each logically multiply the shifted chips from the shift registers
40
#
1
-
40
#n by each pseudo random code C
k
(
0
)-C
k
(N−1) stored therein and output the multiplied results into an adder
50
. Then, the adder
50
receives the multiplied results from the multipliers
30
#
1
-
30
#n and adds in recursive pattern them over a predetermined times, in which initial synchronization may be acquired from a maximum added value out of the accumulated values d
k
.
The active correlator, however, has the problem that causes to prolong initial synchronization time as it processes repeatedly the spread signal to be received by process gain (chip numbers to be multiplied to one bit) of the spread signal. Whereas the passive correlator has the effect that remarkably reduces the initial synchronization time as all the chips of the spread signal are processed simultaneously, but complex construction.
Also, there is disclosed in the U.S. Pat. No. 5,768,306, a sliding correlator used in CDMA systems to establish initial synchronization has memory circuit to store a received signal, to read the received signal at a frequency substantially higher than the storing rate of the received signal and to use the received signal for synchronization, and thereby to reduce initial synchronization time.
The U.S. patent includes the steps of storing the received signal in the memory circuit, reading the received signal at a frequency higher than the strong rate of the received signal, multiplying the received signal by a replica of a spreading code sequence by means of a multiplier, accumulating the output signal of the multiplier by an accumulator over a predetermined time period, deciding the output of the accumulator by a threshold detector whether or not it exceeds a predetermined threshold, shifting the phase of the spreading code sequence when the output of the threshold detector is less than the threshold, and repeating the detection process.
The correlator of the U.S. patent also has the effect that reduces the initial synchronization time, but complex construction.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a complex type correlator in the CDMA system and initial synchronization acquiring method using the same capable of reducing an initial synchronization time while realizing a simple correlator.
In accordance with one aspect of the invention, there is provided a correlator for acquiring initial synchronization, from inputted spread signal of N chips per one bit, that is provided in receiving stages of a base station and a mobile station in a CDMA system characterized by:
a plurality of shift registers for each shifting in turn a spread signal to be received and outputting the shifted signal;
a plurality of multipliers each having a pseudo random code for each logically multiplying the associated shifted spread signal from each shift register by the associated pseudo random code stored therein and outputting the multiplied result;
an adder for adding the multiplied results from each multipliers; and
an accumulator accumulatively adding the added results from the adder over a predetermined times and outputting the accumulated added results.
Also, in accordance with one aspect of the invention, there is provided a method for acquiring initial synchronization using a correlator for acquiring initial synchronization, from inputted spread signal of N chips per one bit, that is provided in receiving stages of a base station and a mobile station in a CDMA system characterized by: the steps of:
shifting in turn a predetermined chips out of a spread signal to be received and outputting the shifted chips, by means of a plurality of shift registers;
logically multiplying each shifted chip from the shift registers by each pseudo random code which is stored in a plurality of multipliers, by means of the multipliers;
adding the multiplied results from the multipliers, by means of an adder;
repeatedly performing accumulative adding the added results from the adder over a predetermined times and outputting the accumulated added results, by means of an accumulator; and
comparing accumulated added results for the all bits of the received spread signal from the accumulator with each other and finding a bit having the most result.


REFERENCES:
patent: 5184135 (1993-02-01), Paradise
patent: 5663983 (1997-09-01), Lin
patent: 5680414 (1997-10-01), Durrant et al.
patent: 5768306 (1998-06-01), Sawahashi et al.
patent: 5956367 (1999-09-01), Koo et al.
patent: 5960048 (1999-09-01), Haartsen
patent: 6088382 (2000-07-01), Maru
patent: 6263011 (2001-07-01), Paik et al.
patent: 6385180 (2002-05-01), Maru
patent: 6411610 (2002-06-01), Li et al.
patent: 6470000 (2002-10-01), Burns et al.

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