Complex multiplier

Details Complex multiplier Complex multiplier

1998-03-24

2001-10-23

Pham, Chi (Department: 2631)

Pulse or digital communications

Miscellaneous

C708S622000, C713S501000

Reexamination Certificate

active

06307907

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a complex multiplier, and more particularly relates to the complex multiplier operating complex multiplication using a multiplier by generating time division signals with a data clock and a clock having a speed twice as fast as the data clock and operating the multiplier in a time division mode by the time division signals.
BACKGROUND OF THE INVENTION
In HDTV (High Definition Television) system, the phase tracking loop is followed by a channel equalizer step. Phase noise is removed, and data correcting the phase noise is outputted to the decoder thereafter.
The phase tracking loop receives I signal (In-phase) from the equalizer, adjusts the gain of the I signal and corrects the phase according to information based on the phase distortion obtained from phase adjustment loop. In the phase adjustment loop, because obtaining the phase distortion from only I signal is impossible, Q(Quadrature) signal is calculated from the I signal. Then, phase distortion occurs due to the two signals. Q signal is obtained by Hilbert-Transforming the I signal. The phase of the complex signal is complemented with complex multiplier. The invention disclosed in U.S. Pat. No. 5,533,070 proposes a simple structure of complex multiplier which is used to find the phase error of I signal. A complex multiplier can operate the complex multiplication.
FIG. 1
shows a prior complex multiplier, which comprises a first register
1
for receiving I value of two complex numbers; a second register
2
for receiving Q value; a third register
3
for receiving cos &thgr;; a fourth register
4
for receiving sin &thgr;; four multipliers
5
,
6
,
7
,
8
for producing four items resulting from the multiplication of two complex numbers applied through the first register
1
to the fourth register
4
; four registers
9
,
10
,
11
,
12
for storing outputs from the four registers
5
,
6
,
7
,
8
; a first subtracter/adder for subtracting or adding the values stored in the two registers
9
,
10
; a second subtracter/adder for subtracting or adding the values stored in the two registers
11
,
12
; first and second shift register
15
,
16
for shifting the values from the first and the second subtracter/adder
13
,
14
; and ninth and tenth registers
17
,
18
for buffering output.
The above mentioned complex multiplier multiplies each item of two complex numbers and adds/subtracts the multiplying results. The detailed description of the complex multiplication is as follows:
If the outputs of complex multiplier are I′, Q′,
I′=I
cos &thgr;−
Q
sin &thgr;  (1)
Q′=I sin &thgr;+
Q
con &thgr;  (2)
Here, I is I input value of N(integer) bits, Q is Q input value of N(integer) bits, cos &thgr; and sin &thgr; are N bits cosine input and N bits sine input. Also, in the equations (1),(2), even number items on the right side represent complex numbers, and symbol j representing complex number is attached but abbreviated.
If I, Q, cos &thgr;, sin &thgr; are correspondingly input to the first though the fourth registers
1
-
4
in sequence as shown in
FIG. 1
, the first multiplier
5
produces I cos &thgr;, the second register
6
Q sin &thgr;, the third register
7
Q cos &thgr;, and the fourth register
8
I sin &thgr;. The multiplication results are each stored in the fifth register
9
though the eighth register
12
in order.
The first subtracter/adder
13
operates “I cos &thgr;+Q sin &thgr;” in equation (1), and the second subtracter/adder
14
operates “I sin &thgr;+Q cos &thgr;” in equation (2). Accordingly, the result of equation (1) is stored in the ninth register
17
, the result of equation (2) is stored in the tenth register
18
, and each result is output respectively.
The prior complex multiplier operating as mentioned in the above description operates each of the multiplications (I cos &thgr;, Q sin &thgr;, I sin &thgr;, Q cos &thgr;) with four multipliers. Therefore, it has problems. Firstly, a number of circuit elements are used in order to comprise four multipliers; secondly, the manufacturing process is complicated much more; and thirdly, due to a number of circuits, the volume is large and the production cost is high.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a complex multiplier for solving the problems.
It is another object of the present invention to provide a the complex multiplier operating complex multiplication using a multiplier by generating time division signals with a data clock and a clock having a speed twice as fast as the data clock and operating the multiplier in a time division mode by the time division signals.
It is another object of the present invention to provide a complex multiplier in which the absolute values of sin &thgr; and cos &thgr; are stored in the memory using complement of the number 2 of sin &thgr; and cos &thgr;, thereby reducing the size of the memory by half.
In order to achieve the above objects of the present invention, complex multiplication is performed using a multiplier by generating time division signals with a first clock and a second clock having a speed twice as fast as the first clock and operating the multiplier in a time division mode by the time division signals. Using a first clock and a second clock, the time division signals delayed by one-forth cycle are generated during one cycle of the first clock. Real element and imaginary element of two complex numbers are stored in D flip flops. A multiplexer driven by the time division signals selects each element of the complex numbers. A multiplier multiplies the selected elements in the selected time order. The multiplication results are latched in a plurality of D flip flops according to the time division signals. The latched multiplication results are added or subtracted with adder and subtracter. The outputs of the adder and subtracter are stored in D flip flops and output from the D flip flops, thereby obtaining the multiplication of two complex numbers.
Furthermore, the absolute values of sin &thgr; and cos &thgr; are stored in memory and subtraction using complements of the number 2 of the absolute values of sin &thgr; and cos &thgr; reduce the size of the memory by half.


REFERENCES:
patent: 3849730 (1974-11-01), Ho
patent: 5440587 (1995-08-01), Ishikawa et al.
patent: 5533070 (1996-07-01), Krishnamurthy et al.
patent: 5621730 (1997-04-01), Kelley

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