Complex matched filter with reduced power consumption

Details Complex matched filter with reduced power consumption Complex matched filter with reduced power consumption

1999-04-06

2002-06-18

Pham, Chi (Department: 2631)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S142000, C708S422000

Reexamination Certificate

active

06408018

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to radio receivers for receiving and despreading direct sequence spread spectrum signals, also known as Code Division Multiple Access (CDMA) signals, and more particularly, to a complex matched filter for use in a receiver which reduces power consumption by using CDMA waveforms using complex despreading codes.
2. Description of Related Art
FIG. 1
illustrates a prior art matched filter type of correlator for correlating real values. A received signal is sampled at a rate Fc samples per second and the samples are entered sequentially to the input of a number of multipliers
10
. Each multiplier
10
includes a second input for receiving a code value C
1
. The present example illustrates a matched filter having a length of
64
. A current input sample Si is multiplied by the code value C
1
in the left most multiplier
10
a
, and the output C
1
.Si is input to a one sample delay element D
1
. The value C
1
.Si emerges from the delay element D
1
during the next sample period when the input sample value S(i+1) is input to the inputs of each of the multipliers
10
. As the value C
1
.Si emerges from the delay element
01
and is applied to the input of a first summer
15
a
, the multiplier
10
b
multiplies input sample S(i+1) by the input code C
2
to obtain a value C
2
.S(i+1). This is applied to the second input of the first summer
15
a
. The output from the summer
15
a
of (C
1
.Si+C
2
.S(i+1)) is input into a second delay element D
2
. This value emerges from the delay element D
2
during the next sample period when S(i+2) is input to the multipliers
10
. The output from D
2
is added to the value C
3
.S(i+2) at summer
15
b
, and the output of summer
15
b
is applied to a first input of delay element D
4
. This process continues in a similar manner until
64
samples have been input to the filter, a value emerges from the rightmost summer
15
and is equal to:
C
1
.S
(
i
)+
C
2
.S
(
i
+1)+
C
3
.S
(
i
+2) . . . +
C
64
.S
(
i
+63)
This equation comprises a
64
sample correlation between the code values C
1
. . . C
64
and the signal samples S(i) . . . S(i+63). After the first
64
samples have been entered, each successive signal sample creates a new
64
point correlation computed in the following manner:
S
(
i
+1) . . .
S
(
i
+64)
S
(
i
+2) . . .
S
(
i
+65) . . . and so forth.
The resulting correlations are a combination of the code symbols C
1
. . . C
64
with 64 signal samples selected according to a sliding window
64
samples wide. Thus this type of matched filter may also be called a sliding correlator.
The matched filter of
FIG. 1
is required to perform 64 multiplications and 63 additions during each sample period of the clock. A complex correlator may employ four of the matched filters of
FIG. 1
to compute the inner products in the equation:
Cr.Sr, Ci.Si, Cr.Si, Ci . . . Sr
where Cr is an N-element vector of the real code symbols, Sr is a vector comprising the real parts of the last N input samples, Ci is an N-element vector of imaginary code symbols and Si is a vector comprising imaginary part of the last N input samples.
The complex correlation of these vectors is given by:
Cr.Sr+Ci.Si; for the real part of the desired correlation;
Cr.Si−Ci.Sr; for the imaginary part of the desired correlation. It is implicitly assumed that the desired correlation is between any N input samples Sr and the complex conjugate of the N sample code (Cr, Ci), thus giving rise to the exemplary choice of plus and minus signs in the above example.
Prior art filters for producing complex correlation values use four of the above described matched filter, thus requiring, 4N multiplication processes, 4(N−1) addition processes and 4(N−1) delay elements in order to achieve the complex correlation value. If some method could be found to reduce the number of multiplication, addition and delays performed to obtain each successive correlation value, a dramatic reduction in the power consumed by the equipment forming the complex correlations would be realized. In applications such as cellular telephones where battery life considerations are paramount such a solution would be of great benefit.
SUMMARY OF THE INVENTION
The present invention overcomes the foregoing and other problems with a matched filter for computing complex correlations between a sequence of complex input samples and a complex code which utilizes less additions and multiplications than those utilized in currently existing complex matched filter. The matched filter includes a set of N changeover switches. The switches each have a first input connected to the real value portion of the input sample values and a second input connected to the imaginary values portion of the input sample values. A control input receives control signals controlling a pair of outputs from the changeover switches. In response to application of a control signal in a first state, the real values are output over a first output of the changeover switches and the imaginary values are output on the second output of the changeover switch. When the control signal moves to a second state the situation is reversed such that imaginary values are output on the first output and real values are output on the second output.
The first outputs of the set of N changeovers are connected with a matched filter portion for generating a real portion of a complex correlation. A first set of N multipliers are connected to the first outputs of the changeover switches. A second input of the N multipliers are connected to receive real symbols of a complex code. The multiplied outputs are applied to the first set of (N−1) adders which add the multiplied outputs of the N multipliers with a corresponding delayed sum to generate an undelayed sum. A set of (N−1) delay elements delay the undelayed sums to produce delayed sums. The first of the undelayed sums comprises an output of the first multiplier rather than an output of an adder. The output of a last adder comprises the real portion of the complex correlation. A second matched filter portion is coupled to the second output of the N changeover switches and is configured in a similar manner as the first matched filter portion. The second matched filter generates the imaginary portion of the complex correlation from the last adder.


REFERENCES:
patent: 5365549 (1994-11-01), Kazecki
patent: 5999562 (1999-12-01), Hennedy et al.
patent: 6005887 (1999-12-01), Bottomley et al.
patent: 6130906 (2000-10-01), Davidovici et al.
patent: 00/08985 (2000-07-01), None
Norm Couturier, James Wight and Leroy Pearce, “Experimental Results for Four-Pase Digital Matched Filtering of Spread-Spectrum Waveforms”,IEEE Transactions on Communications, vol. COM-34, No. 8, Aug. 1986, XP002108864, pp. 836-840.
Rolf Nauerz and Herbert Bauer, “The Suitability of Modern CMOS Gate Array Circuits as Correlators and Matched Filters for Spread-Spectrum Signals”, Proceedings of the Military Communications Conference, (MILCOM), US, New York, IEEE, vol. CONF. 6, 1987, XP000124771, pp. 473-478.

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