Complex logical fault detection apparatus and method

Details Complex logical fault detection apparatus and method Complex logical fault detection apparatus and method

1978-03-01

1979-07-17

Smith, Jerry

Registers

Systems controlled by data bearing records

Time analysis

324 73R, G06F 1100

Patent

active

041612760

ABSTRACT:
The present invention relates to apparatus and method for testing logic circuit boards for complex logical faults contained therein. A known good identical logic circuit is stimulated by a preselected sequence of binary test patterns and the number of transitions in logical state before achieving a final logical state as well as the final logical state for a number of points within the circuit are monitored and saved. The logic circuit being tested is then stimulated by the same test pattern sequence and the number of transitions and final logical states achieved are compared. Failure to have identity between the known good logical circuit and the logical circuit being tested both as to number of transitions and final logical state achieved for the tested points indicates a malfunction within the board which would not be detected by mere sampling of the final output state alone.

REFERENCES:
patent: 3887869 (1975-06-01), Connolly et al.
patent: 3924181 (1975-12-01), Alderson
patent: 3976864 (1976-08-01), Gordon et al.
patent: 4059749 (1977-11-01), Feilchenfeld

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