Complex despreading system

Details Complex despreading system Complex despreading system

1998-04-06

2001-06-26

Chin, Stephen (Department: 2634)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S142000, C375S150000, C375S261000, C375S298000, C370S320000

Reexamination Certificate

active

06252899

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a complex despreading system used in a receiver with direct-sequence code-division multiple-access (DS-CDMA) communication system.
BACKGROUND OF THE INVENTION
The development of mobile land communications has seen DS-CDMA gain importance in wideband mobile communications and Local Area Networks (LAN) because it is adequate for multimedia communications due to its changeable transmission speed. DS-CDMA performs primary and secondary modulations to modulate information into narrowband, and to spread the spectrum into wideband by spread codes, respectively.
In one type of DS-CDMA communication system, data to be transmitted is modulated in both primary and secondary modulations in the manner of Quadrature Phase-Shift Keying (QPSK). Two different spread code sequences are defined for in-phase and quadrature components of a carrier wave, and the data to be transmitted is divided into the in-phase and quadrature components. This is expressed by complex vectors in formulas (1) and (2), in which I is an information vector and C is a spread-code vector:
I=I
i+j·I
q
  (1)
C=C
i+j·C
q
  (2)
Here, Ii is an in-phase component, and Iq is a quadrature-phase component of the information I.
In the primary QPSK modulation, the carrier wave is modulated by Ii into in-phase components of the carrier wave by Ii, and it modulates the carrier wave into quadrature components by Iq. In the secondary QPSK modulation, a spread transmission signals is generated by spreading modulation using spread-code C, as shown in formulas (3) and (4):
S
i=I
i·C
i−I
q·C
q
  (3)
S
q=I
i·C
q=I
q·C
i
  (4)
When the noise on the transmission route is ignored, a signal R to be received at the receiver side is equal to S which is shown in formulas (5) and (6):
R
i=I
i·C
i−I
q·C
q
  (5)
R
q=I
i·C
q+I
q·C
i
  (6)
The receiving system performs despreading using complex conjugate code vector (Ci−j·Cq) of C on transmission. The received signal after despreading is shown in formula (7), using (5) and (6):
D=Di+i·Dq=
(
Ri+j·Rq
)·(
Ci−j·Cq
)=(
Ri·Ci+Rq·Cq
)+j·(−
Ri·Cq+Rq·Ci
)   (7)
When Ci=Cq in the formula above, the secondary modulation is Binary Phase-Shift Keying (BPSK). In this case, the received signal in the receiving system after despreading is expressed in formula (8), as derived from (7):
D=Di+i·Dq=
(
Ri·Ci+Rq·Ci
)+j(−
Ri·Ci+Rq·Ci
)   (8)
It is proposed for a DS-CDMA mobile and personal communication system that data is modulated by QPSK in both primary and secondary modulations on the upward transmission line from a mobile station to the base station, and by QPSK in the primary modulation and BPSK in the secondary modulation on the downward transmission line from base to mobile station. The secondary modulation of QPSK in the downward line makes the transmission tough against distortion caused by a power amplifier in the transmitter. However, the processing in the receiving system becomes complicated.
FIG. 5
shows a block diagram the conventional complex despreading system for the DS-CDMA system above. A complex matched filter, designated by reference numbers
10
and
11
, is used for despreading received signals which is modulated by the primary modulation of QPSK and by the secondary modulation of BPSK. In
FIG. 5
, the conventional despreading system includes a distributor
1
, multiplication circuits
2
and
3
, a carrier wave generator
4
, a &pgr;/2 phase shifter
5
, Low-Pass Filters (LDP)
6
and
7
, adders
8
and
9
, an I-channel multiplication and addition circuit
10
, a Q-channel multiplication and addition circuit
11
, and a spread-code register
12
.
A received signal is distributed into two lines by the distributor
1
and quadrically detected by the multiplication circuit
2
and
3
. The signal on the first line is multiplied by a carrier wave from the carrier wave generator
4
in the multiplication circuit
2
, then the carrier wave is deleted from the multiplication result through the low-pass filter
6
. The signal on the second line is multiplied at multiplication circuit
3
by a carrier wave shifted by &pgr;/2 in phase by the phase shifter
5
, then the carrier wave is deleted from the multiplication result through the low-pass filter
7
. Therefore, the received signal is quadrically demodulated into a baseband signals on the two lines. The baseband signals Ri and Rq are input to the complex matched filter including consisting of multiplication and addition circuits
10
and
11
. To simplify the description, the intermediate frequency amplifying stage is neglected.
The circuits
10
and
11
are matched filters for I-channel and Q-channel, to each of which the in-phase component of spread-code Ci is input from the spread-code register
12
. The circuits multiply Ri and Rq by Ci, respectively, and calculate the total sum of the multiplication products, respectively so as to despread the signal on the two lines. These are correlation calculations of Ri·Ci and Rq·Cq, respectively. The adders
8
and
9
output the correlation value of Di=Ri·Ci+Rq·Ci and Dq=−Ri·Ci+Rq·Ci defined in the formula (8), respectively.
Then, the despread corresponding to the secondary modulation of BPSK is completed. So, the in-phase component Di and the quadrature component Dq of the received signal are obtained corresponding to Ii and Iq. According to Di and Dq, Ii and Iq can be reproduced. It will be understood that a complex despread is performed by the system consisting of circuits
8
,
9
,
10
and
11
.
FIG. 6
is an exemplary block diagram of the I- and Q-channel multiplication and addition circuit in FIG.
5
. In
FIG. 6
components,
51
a
to
51
f
are sampling and holding circuits,
52
is a controller, component
53
a
to
53
f
are multiplication circuits, component
54
is a reference voltage generator, component
55
is a spread-code register, and components
56
to
61
are adders.
Although the circuit in
FIG. 6
has six-chip spread-code sequences and six-steps delay stages for easy understanding, the actual spread-code sequence is much longer than this, and the necessary processing stages have to be set according to the length of the spread-code sequence. This multiplication and addition circuit is a matched filter circuit with small size and low power consumption.
In
FIG. 6
, the received baseband signal corresponds to Ri or Rq in FIG.
5
. This signal is successively distributed to each of the sampling and holding circuits
51
a
to
51
f
by the controller
52
for controlling a sampling timing of the sampling and holding circuits
51
a to
51
f. The output from each of the sampling and holding circuits
51
a to
51
f is multiplied by the spread-code supplied from the spread-code register
55
in the multiplication circuits
53
a to
53
f, respectively. The outputs of the multiplication circuits are classified into four groups and the outputs of the groups are added together in the adders
56
to
59
, respectively. A correlation value is finally obtained by adding the addition result of the adders
56
to
59
by the adders
60
and
61
. A reference voltage Vr is input from the reference voltage generator to the multiplication circuits
53
a
to
53
f
for a voltage reference of the multiplication calculations, as described below.
Sampling and holding circuits
51
a
to
51
f
use analog computation circuits, which include analog switches, input capacitances, inverting amplifiers, and so on. The inverting amplifiers are structured by serially connecting CMOS inverters in three stages, with feedback capacitances (not shown) between their input and output terminals.
The inverting amplifiers works in the liner transition area of input-output performance of the CMOS inverters. As shown in the block of the sampling and holding circuit

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