Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2006-08-29
2006-08-29
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S141000, C375S247000
Reexamination Certificate
active
07098828
ABSTRACT:
A complex band-pass ΔΣ AD modulator is provided with a subtracter device, a complex band-pass filter, first and second AD converters, and first and second DA converters. The first and second DA converters and first and second logic circuits are sandwiched by first and second multiplexers. At a first timing of a clock signal, the first multiplexer inputs and outputs the first and second digital signals as they are, and at a second timing thereof, the first multiplexer inputs the first and second digital signals, and outputs the first digital signal as a second digital signal and outputs the second digital signal as a first digital signal. The second multiplexer inputs and outputs first and second analog signals similarly. The first and second logic circuits substantially noise-shapes non-linearities of the first and second DA converters by realizing complex digital and analog filters, using high-pass and low-pass element rotation methods.
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F. Henkel, et al., “A 1-MHz-Banwidth Second-Order Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for Low-IF Radio Receivers”, IEEE Journal of Solid-State Circuits, vol. 37, pp. 1628-1635, Dec. 2002, no date.
F. Esfahani, et al., “A fourth Order Continuous-Time Complex Sigma-Delta ADC for Low-IF GSM and EDGE Receivers”, Symposium of VLSI Circuits, Digest of Technical Papers, pp. 75-78, Jun. 2003, no date.
R. Schreier, et al., “A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth”, IEEE Journal of Solid-State Circuits, vol. 37, pp. 1636-1644, Dec. 2002, no date.
T. Salo, et al., “A dual-Mode 80 MHz bandpass ΔΣ modulator for a GSM/WCDMA IF- Receiver”, ISSCC Digest of Technical Papers vol. 45, pp. 218-219, Feb. 2002, no date.
S.A. Jantzi, et al., “Quadrature bandpass ΔΣ Modulation for Digital Radio,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 1935-1950, Dec. 1997, no date.
S. R. Norsworthy, et al. (editors), “Delta-Sigma Data Converters, —Theory, Design, and Simulation”, IEEE Press, 1997, no month.
T. Ueno, et al. “A fourth-Order Bandpass ΔΣ Modulator Using Second-Order Bandpass Noise-Shaping Dynamic Element Matching”, IEEE Journal of Solid-State Circuits, vol. 37, pp. 809-816, Jul. 2002, no date.
T. Shui, et al. “Mismatch Shaping for a Current-Mode Multibit Delta-Sigma DAC”, IEEE Journal of Solid-State Circuits, vol. 34, pp. 331-338, Mar. 1999, no date.
L. R. Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters”, IEEE Journal of Solid-State Circuits, vol. 24, pp. 267-273, Apr. 1989, no date.
E. Fogleman, et al., “A 3.3-V Single-Poly CMOS Audio ADC Delta-Sigma Modulator With 98.dB Peak SINAD and 105-dB Peak SFDR”, IEEE Journal of Solid-State Circuits, vol. 35, pp. 297-307, Mar. 2000, no date.
R. Schreier, et al., “Speed vs. Dynamic Range Trade-Off in Oversampling Data Converters”, in C. Toumazou et al. (editors), Trade-Offs in Analog Cir
Kobayashi Haruo
San Hao
Wada Atsushi
Wada Hiroki
Semiconductor Technology Academic Research Center
Wamsley Patrick
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