Complex arithmetic processor and method

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364748, G06F 738

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active

054735572

ABSTRACT:
A complex arithmetic processor and method includes a host interface for distributing data, a left memory and a right memory each coupled to the host interface, and a Z memory coupled to the host interface. The left memory and the right memory store the data and the Z memory stores Z memory data. A right/left switch is coupled to the left memory and to the right memory and makes left memory a data source and a right memory a data destination in a first setting, and makes the right memory the data source and the left memory the data destination in a second setting. An arithmetic engine is coupled to the host interface, to the Z memory, and to the left and right memories. The arithmetic engine uses the data and the Z memory data to perform an operation on the data to produce a result.

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An article entitled "Frequency Domain Array Processor", Preliminary User's Guide Revision Mar. 1991, Array Microsystems, Colorado Springs, Colo., including sections I-V.

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