Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-01-11
2001-08-28
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C257S295000, C257S532000, C438S239000, C438S381000
Reexamination Certificate
active
06281023
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to ferroelectric capacitors. More particularly, the present invention relates to a technique and structure for preventing degradation in the electrical performance of ferroelectric capacitors.
A portion of a prior art integrated circuit ferroelectric memory cell
10
including a transistor and a ferroelectric capacitor is shown in
FIG. 1. A
silicon or other substrate
12
includes a diffused region
14
, which forms part of a transistor used in the memory cell. A thick oxide layer
16
forms the substrate for the ferroelectric capacitor. The thick oxide layer
16
is patterned and etched to allow access to diffused region
14
. The ferroelectric capacitor includes a platinum bottom electrode
18
, a ferroelectric layer
20
, typically PZT (lead zirconate titanate), and a platinum top electrode
22
. A subsequent oxide layer
24
is deposited, which is patterned and etched, to provide access to diffused region
14
, bottom electrode
18
, and to top electrode
22
. A local interconnect layer
26
is deposited, patterned and etched, to provide a local interconnect
26
A between top electrode
22
and diffused region
14
, as well as metalization
26
B for bottom electrode
18
.
It is well known in the ferroelectric arts that certain ferroelectric materials, particularly PZT, are susceptible to degradation of electrical switching performance if exposed to hydrogen. One source of hydrogen can be found in the plastic packaging materials often used with integrated circuits. Another source of hydrogen can be found in the various oxide layers used in fabricating the ferroelectric capacitor or memory cell.
A section
28
of memory cell
10
is shown in greater magnification in
FIG. 2
to illustrate the problem of hydrogen sensitivity that exists within the prior art memory cell. Section
28
shows oxide layer
16
, bottom electrode
18
, ferroelectric layer
20
, top electrode
22
, oxide layer
24
, and local interconnect
26
A. Note particularly in
FIG. 2
that there is an interface between oxide layer
24
and ferroelectric layer
20
. The interface extends along the top surface and sides of ferroelectric layer
20
. During and after fabrication, hydrogen is generated within oxide layer
24
, which in turn is gradually absorbed by ferroelectric layer
20
. The arrows shown in
FIG. 2
show generally the probable path of hydrogen diffusion into the ferroelectric layer
20
. Studies have shown that exposure to hydrogen gradually degrades the amount of switching charge produced by the ferroelectric capacitor. Over time, the exposure to hydrogen may destroy electrical switching performance altogether.
What is desired, therefore, is a technique and structure to reduce hydrogen sensitivity in an integrated ferroelectric capacitor.
SUMMARY OF THE INVENTION
It is, therefore, a principal object of the present invention to improve the electrical switching performance of integrated circuit ferroelectric capacitors by reducing sensitivity to hydrogen.
It is another object of the invention to improve the performance of ferroelectric memory circuits.
It is an advantage of the invention that the fabrication methods set forth are generally compatible with existing ferroelectric capacitor and ferroelectric memory fabrication methods.
It is another advantage of the invention that the capacitor fabricated as set forth herein can be used in a wide array of electronic products such as integrated circuit memories and other integrated circuits, RF/ID integrated circuits and cards, discrete devices, or any application in which improved electrical switching performance and resistance to hydrogen diffusion is desired.
According to a first general embodiment of the present invention, a ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.
According to a second general embodiment of the present invention, a ferroelectric capacitor includes a bottom electrode and a ferroelectric layer formed on the bottom electrode. The ferroelectric layer is partially etched to form an indentation to receive a top electrode. A dielectric layer is formed over the ferroelectric layer, and includes a contact hole to allow metalization of the top electrode. The partial encapsulation of the top electrode also reduces the sensitivity of the ferroelectric capacitor to hydrogen.
The ferroelectric layer in the capacitor can be fabricated using PZT, SBT, or other known ferroelectric materials. The ferroelectric capacitor can then be used in conjunction with a transistor to form a memory cell in an array of such cells.
A first method of fabricating a ferroelectric capacitor according to the present invention includes the steps of: forming in sequence a bottom electrode layer, a first ferroelectric layer, and a top electrode layer; etching the top electrode layer to form a top electrode; forming a second ferroelectric layer over the first ferroelectric layer, thereby completely encapsulating the top electrode; etching the second ferroelectric layer; etching the first ferroelectric layer and the bottom electrode layer to form a bottom electrode; forming a dielectric layer over the etched first ferroelectric and second ferroelectric layers; etching a contact hole through the dielectric layer and the second ferroelectric layer to allow metalization of the top electrode; and etching a contact hole through the dielectric layer and the first ferroelectric layer to allow metalization of the bottom electrode.
A second method of fabricating a ferroelectric capacitor according to the present invention includes the steps of: forming in sequence a bottom electrode layer, a first ferroelectric layer, and a top electrode layer; etching the top electrode layer to form a top electrode; etching the first ferroelectric layer; etching the bottom electrode layer to form a bottom electrode; forming a second ferroelectric layer over the first ferroelectric layer, thereby completely encapsulating the top electrode; etching the second ferroelectric layer so that the second ferroelectric layer overlaps the bottom electrode; forming a dielectric layer over the etched second ferroelectric layer; and etching contact holes through the dielectric layer and the second ferroelectric layer to allow metalization of the top and bottom electrodes.
A third method of fabricating a ferroelectric capacitor according to the present invention includes the steps of: forming in sequence a bottom electrode layer, a first ferroelectric layer, and a top electrode layer; etching the top electrode layer to form a top electrode; etching the first ferroelectric layer; etching the bottom electrode layer to form a bottom electrode; forming a second ferroelectric layer over the first ferroelectric layer, thereby completely encapsulating the top electrode; forming a dielectric layer over the second ferroelectric layer; and etching contact holes through the dielectric layer and the second ferroelectric layer to allow metalization of the top and bottom electrodes.
A fourth method of fabricating a ferroelectric capacitor according to the present invention includes the steps of: forming in sequence a bottom electrode layer, a first ferroelectric layer of a first thickness, and a top electrode layer; etching the top electrode layer to form a top electrode; etching the first ferroelectric layer; forming a second ferroelectric layer of a second thickness over the first ferroelectric layer, thereby completely encapsulating the top electrode; etching the second ferroelectric layer and the bottom electrode layer to form a bottom electrode; forming a dielectric layer over the etched second ferroelectric layer; and etching contact holes through the dielectric layer a
Eastep Brian Lee
Evans Thomas A.
Chaudhuri Olik
Hogan & Hartson LLP
Kubida, Esq. William J.
Meza Peter
Pizarro-Crespo Marcos D.
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