Completely complementary MOS memory cell with tunneling through

Details Completely complementary MOS memory cell with tunneling through Completely complementary MOS memory cell with tunneling through

1995-05-23

1997-01-14

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518508, 36518529, G11C 1604

Patent

active

055946879

ABSTRACT:
Circuitry added to CMOS memory cell configured to enable tunneling through its PMOS and NMOS transistors, the circuitry preventing leakage current during programming. The circuitry includes a separate NMOS pass gate for connecting the source of the NMOS transistor of the CMOS cell to Vss. The gate of the NMOS pass gate is controlled to turn off the NMOS transistor during programming through the PMOS transistor to prevent current loss on the Vss line. The NMOS pass gate further provides a means for enabling or disabling the NMOS transistor making the CMOS cell useful as an array cell for a PAL device.

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