Television – Camera – system and detail – Combined image signal generator and general image signal...
Reexamination Certificate
1998-11-10
2003-03-04
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Combined image signal generator and general image signal...
C348S243000, C348S308000, C348S533000
Reexamination Certificate
active
06529237
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention pertains in general to a front end sample and hold and signal conditioning circuit for processing a CCD signal prior to converting it to a digital format and, more particularly, to a signal conditioning circuit that provides a number of integrated functions such as correlated double sampling (CDS) and programmable gain.
BACKGROUND OF THE INVENTION
Charge coupled devices (CCD) have been utilized in a number of image generators such as video cameras and optical scanners. The signal typically output by such devices is an analog signal, which is then processed, typically in the digital domain. These analog signals are typically input to some type of analog-to-digital conversion device, which will then perform the necessary processing thereon. However, prior to input of the analog signal to the A/D converter, it typically must have some type of signal conditioning performed thereon.
For a circuit processing AC coupled CCD signals, some type of sample and hold and signal conditioning circuit is required. One requirement is to perform some type of sampling operation, such as a correlated double sampling (CDS) to enhance signal-to-noise ratio of the CCD signals. Further, this could be a simple sample and hold function. Since it is an AC coupled system, there is a DC level for the input signal that is unknown. The signal conditioning circuit must somehow determine this DC signal. Further, dynamic range will be enhanced with some type of programmable gain. Another requirement for a front end is to provide some type of DC offset that will eliminate what is referred to as “dark current,” which is the difference between an output signal with no level, i.e., representing dark, and the actual perceived signal. If there is an offset, this will not provide a true dark signal. Some type of offset calibration is required to accommodate this adjustment.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein comprises a preconditioning circuit for preconditioning an analog CCD output signal representing the output of a plurality of pixels, with each pixel having associated therewith a DC reference level and a video level. An amplifier is provided with an associated gain which has associated therewith a sampling network. The sampling network is operable to sample a CCD output signal onto the input of the amplifier to provide a sampled analog output signal from the amplifier. An offset network is provided for generating a predetermined analog offset signal level and then offsetting the sampled input signal to the input of the amplifier by the predetermined analog offset signal level. This offset operation will remove any error due to both dark current errors in the CCD output signal and any offset errors in the amplifier.
In another aspect of the present invention, the sampling network operates in accordance with a correlated double sampling algorithm. The sampling network is operable to receive a single ended input in the form of a CCD output signal and then convert it to a double ended output from the amplifier. Two input sampling capacitors are provided for sampling the input signal onto one of two differential inputs with the amplifier being a differential amplifier. The DC reference level is sampled onto the first sampling capacitor during the generation thereof and, at a later time, the video signal level is sampled onto the second sampling capacitor. By equalizing the plates of the capacitors opposite to the positive and negative inputs of the amplifier, a differential input signal is provided on the differential input to the amplifier.
In a further aspect of the present invention, a clamping circuit is provided for clamping the CCD output signal to a known DC clamp voltage during the time the DC reference level is generated. This allows the DC reference level sampled onto the first sampling capacitor to be a known DC reference level for each pixel.
In an even further aspect of the present invention, feedback capacitors are provided which, in conjunction with the sampling capacitors, define the gain of the amplifier. Each of the sampling capacitors has associated therewith a trimming network for varying the overall effective capacitance of the input sampling capacitor.
REFERENCES:
patent: 5724095 (1998-03-01), Shyu et al.
patent: 6018364 (2000-01-01), Mangelsdorf
patent: 6166766 (2000-12-01), Moore et al.
patent: 6201572 (2001-03-01), Chou
patent: 6346968 (2002-02-01), Domer et al.
Matsumoto et al. A CMOS fron-end for CCD cameras, IEEE, pp. 186-187, 1996.*
Hyabg et al., Reduced nonlinear distortion in circuits with correlated double sampling, IEEE, pp. 159-162, 1996.*
Wang et al., Capacitive ration testing and sensor readout, IEEE, pp. 1169-1172, May 19-21, 1997.
Loloee Arash
Soenen Eric G.
Tsay Ching-yuh
Brady III W. James
Garber Wendy R.
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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