Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1996-08-21
1998-02-03
Fahmy, Wael
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257525, 257511, 257586, 257526, 257623, H01L 218228
Patent
active
057147930
ABSTRACT:
A method is described for fabricating a complementary, vertical bipolar sconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.
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Cartagena Eric N.
Walker Howard W.
Fahmy Wael
Fendelman Harvey
Hardy David B.
Kagan Michael A.
Lipovsky Peter A.
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