357 51, H01L 2702
A complementary type semiconductor integrated circuit device includes a semiconductor substrate of a first conductivity type connected to a high potential input terminal, a first well region and a second well region, both of a second conductivity type and formed selectively on a surface of the substrate. The well regions are connected to a high potential input terminal and a low potential input terminal, respectively. A diffusion region of the first conductivity type is formed selectively on a surface of the second well region. A capacitor having capacitance of a value larger than a capacitance between the high potential input terminal and the intermediate potential input terminal, whereby if the high and intermediate potentials are supplied to the high and intermediate input terminals and the low potential is not supplied to the low potential input terminal, it is possible to prevent electrons from flowing to the second well region from the diffusion region. Consequently, no latch-up occurs even when the low potential is supplied after the high potential and intermediate potentials have been supplied.
patent: 4868627 (1989-09-01), Yamada et al.
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