Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
2002-06-05
2003-09-09
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S333000, C327S218000, C326S068000, C326S081000
Reexamination Certificate
active
06617896
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a complementary signal generation circuit, and relates in particular to a complementary signal generation circuit for receiving a signal and for generating, for the input signal, a complementary signal that includes an in-phase signal and an antiphase signal.
2. Description of the Prior Arts
Recently, signal transfer speeds have been increased, and fast operations exceeding 1 GHz are required for an input/output buffer. LVDS (Low-Voltage Differential Signaling), known as a fast signal transmission/reception circuit, is a technique employed for transferring data using a complementary signal that includes an in-phase signal and an antiphase signal having a small amplitude of about 0.4 V. LVDS is characterized by providing excellent noise resistance, low power consumption and high-speed operation; however, LVDS also has two problems. The first problem is waveform distortion caused by jitter, and the second problem is waveform distortion due to the fluctuation of a transistor characteristic, such as a threshold voltage, that is caused by the primary manufacturing factor.
According to the first problem, since with LVDS complementary signals are transmitted along a pair of signal lines, not only does jitter occur in a reception circuit, but also the jitter may cause the phase of a complementary input signal to shift in the opposite direction, so that it is difficult for an output signal cross point, a term used to designate a point whereat an in-phase signal and an antiphase signal intersect, to be located and maintained near a position representing 50% of the amplitude of the signals.
Generally, eye pattern standards are specified for a fast interface, such as SONET/SDH, InfiniBand or FiberChannel, and cross point locations are set so they are near locations representing 50% of the amplitude of signals. An eye pattern method is employed to observe a target signal by superimposing an eye pattern on a clock cycle. Using this method, it is possible to efficiently observe the waveform distortion of an input signal and the fluctuation of an output waveform that are caused, for example, by jitter or a signal delay that occurs as the result of amplification.
FIG. 1A
is a diagram showing the fluctuation of an output waveform due to jitter and a shaded area, defined by the eye pattern standards, that the waveform should not overlap. If a cross point can not be maintained at a location near the 50% point of the amplitude of the signals, the eye pattern will be distorted and the standards will not be satisfied.
As is shown in
FIG. 1A
, according to LVDS, a signal transmission is delayed by the effect of jitter, and when the fluctuation direction differs for both complementary signals, a cross point P
81
is moved to P
82
, and a cross point P
83
is moved to P
84
. Since the cross points are greatly shifted from locations near the 50% point of the amplitude signals, the adjustment of the cross points is difficult.
The second problem is that, as is shown in
FIG. 1B
, the inclination of the leading/falling edge of an output signal fluctuates due to the characteristic change that is caused by a primary manufacturing factor. Since the fluctuation of the inclination due to the characteristic change that is caused by the manufacturing factor is large, and the fluctuation direction may differ for both complementary signals, cross points may be generated at various positions, such as P
91
to P
95
, or no cross point may be generated, so that a satisfactory margin relative to the eye pattern standards can not be obtained.
An explanation has been given that a circuit, such as an LVDS circuit, for inputting a complementary signal and outputting a complementary signal is greatly affected by jitter. On the other hand, for a complementary signal generation circuit for receiving one signal and for generating and outputting an in-phase signal and an antiphase signal thereof, when jitter affects an input signal, both the output in-phase signal and the output antiphase signal are moved in the same direction. Thus, although jitter occurs in the complementary signal generation circuit due to the interaction between inverters
15
,
16
and
17
and a parasitic element, compared with the LVDS circuit, the jitter will produce only small a effect, which is the factor of the distortion of the eye pattern.
FIG. 2
is a circuit diagram showing a first conventional complementary signal generation circuit. An input signal
101
is passed through inverters
15
and
16
, and is output as an in-phase signal
103
, and is also passed through the inverters
15
,
16
and
17
, and is output as an antiphase signal
102
.
In the complementary signal generation circuit in
FIG. 2
, the effect produced by the jitter and the distortion of the eye pattern is smaller than that for the LVDS. However, in the complementary signal generation circuit shown in
FIG. 2
, the number of inverter stages from the input to the in-phase output differs from the number of inverter stages from the input to the anti-phase output, i.e., in the first case it is two and in the second it is three. Thus, the output waveform fluctuates due to the characteristic change caused by the manufacturing factor, and distortion of the eye pattern occurs. In order to locate the cross point near the 50% point of the amplitude, the sum of the delay of the inverter
17
and the delay produced by the inverter
18
must be substantially equal to the delay produced by the inverter
16
, so that the inclination of the change of the in-phase signal
103
must be much greater than the inclination of the change of the antiphase signal
102
. Accordingly, the change in the inclination of the in-phase signal
103
accompanied by the characteristic variance of the transistor would be increased.
As a second conventional example, there is a complementary signal generation circuit wherein the number of gate stages from the input to the antiphase output is equal to the number of gate stages from the input to the in-phase output.
FIGS. 3A and 3B
are circuit diagrams showing a complementary signal generation circuit disclosed in Japanese Patent Laid-Open No. 03-258015. As is shown in
FIG. 3A
, an inverter
81
and a buffer circuit
82
constitute a complementary signal generation circuit, and a signal
101
is input to the inverter
81
and the buffer circuit
82
. The inverter
81
inverts the input signal
101
, and generates an antiphase signal
102
, while the buffer circuit
82
uses the input signal
101
to generate an in-phase signal
103
.
As is shown in
FIG. 3B
, the inverter
81
is so designed that a p channel MOS transistor Qp
21
and an n channel MOS transistor Qn
21
are connected in series between a power source and the ground, and the buffer circuit
82
is so designed that an n channel MOS transistor Qn
22
and a p channel MOS transistor Qp
22
are connected in series between a power source and the ground.
In the complementary signal generation circuit in
FIGS. 3A and 3B
, since the input signal
101
is transmitted along a signal path formed of a single logical stage provided by either the inverter
81
or the buffer circuit
82
, theoretically the delays produced along the signal path by these two components are equal, and the start time of the change point is the same for the antiphase signal
102
and the in-phase signal
103
.
However, in actuality, since the absolute value of the gain of the inverter
81
is large near the point representing 50% of the amplitude, while the absolute value of the gain of the buffer circuit
82
is small, the response to a change in the input signal
102
differs between the inverter
81
and the buffer circuit
82
. Therefore, in the second conventional complementary signal generation circuit, when a transistor characteristic, such as a threshold voltage, is changed due to a manufacturing factor, the delay and the inclination of the waveform vary for each complementary signal, and it is difficult to adjust a cross point so as to s
Aoki Mikio
Uenishi Yasutaka
Cunningham Terry D.
Foley & Lardner
NEC Electronics Corporation
Nguyen Long
LandOfFree
Complementary signal generation circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Complementary signal generation circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary signal generation circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3080444