Complementary semiconductor memory device including cell access

Details Complementary semiconductor memory device including cell access Complementary semiconductor memory device including cell access

1989-11-01

1991-09-24

Gossage, Glenn

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365149, 365181, 307449, 307451, G11C 11407

Patent

active

050519590

ABSTRACT:
A complementary semiconductor memory device comprises a memory cell array (73, 100) in which each cell (MC.sub.p ; MC.sub.po) has a first MIS transistor (Q.sub.p); Q.sub.p1, Q.sub.p2) of a first conduction type connected to a word line, a decoding circuit (71) for decoding an input address signal and generating a selecting signal, and a driving circuit (72; 90) having a second MIS transistor (W.sub.80) of a second conduction type opposite to the first conduction type for driving the word line, thereby improving the operation speed thereof, while decreasing the possibility of the destruction of information in each cell by .alpha.-rays. A word drive signal having a negative potential may be used, and the threshold voltage of the second MIS transistor is selected to be greater than an absolute valve of the threshold voltage of the first MIS transistor.

REFERENCES:
patent: 4156940 (1979-05-01), Hollingsworth et al.
patent: 4189782 (1980-02-01), Dingwall
patent: 4628486 (1986-12-01), Sakui
patent: 4697252 (1987-09-01), Furuyama et al.
Katsuhiro Shimohigashi et al., "An n-Well CMOS Dynamic RAM", 8107 IEEE Journal of Solid-State Circuits, vol. SC-17 (1982) Apr., No. 2, New York, pp. 344-348.
Roger G. Stewart, "High Density CMOS ROM Arrays," 1977 IEEE International Solid-State Circuits Conference, vol. 20, No. 20, Feb. 1977, pp. 20-21.
R. I. Kung et al., A Sub 100ns 265 K Dram in CMOS III Technology, pp. 278-279, Digest of Tech. Paper of ISSCC, Feb. '84.

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