Complementary pass gate logic implementation of 64-bit...

Details Complementary pass gate logic implementation of 64-bit... Complementary pass gate logic implementation of 64-bit...

2007-03-20

2007-03-20

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S714000

Reexamination Certificate

active

10278440

ABSTRACT:
An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.

REFERENCES:
patent: 6496846 (2002-12-01), Bradley
patent: 6954773 (2005-10-01), Liu
patent: 2003/0061253 (2003-03-01), Evans
patent: 2003/0088603 (2003-05-01), Wallace
patent: 2003/0229661 (2003-12-01), Kim et al.
patent: 2004/0073592 (2004-04-01), Kim et al.

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