Complementary output, high-density CMOS decoder/driver circuit f

Details Complementary output, high-density CMOS decoder/driver circuit f Complementary output, high-density CMOS decoder/driver circuit f

1988-02-29

1989-06-27

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307452, 307463, 307481, 36523006, H03K 19096

Patent

active

048432610

ABSTRACT:
A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .phi.PC line is included for receiving a .phi.PC precharge clock signal thereon and a .phi.R line is provided for receiving a .phi.R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node of the decoder and to AN and AN lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the AN line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line and is further responsive to the second selection signal to provide an output signal on a second memory word line.

REFERENCES:
patent: 4194130 (1980-03-01), Moench
patent: 4308526 (1981-12-01), Smith
patent: 4309629 (1982-01-01), Kamuro
patent: 4471240 (1984-09-01), Novosel
patent: 4514829 (1985-04-01), Chao
patent: 4584674 (1986-04-01), Watanabe
patent: 4618784 (1986-10-01), Chappell et al.
patent: 4635233 (1987-01-01), Matsumoto et al.
patent: 4725742 (1988-02-01), Tachimori et al.
"Improved Decode Circuits for CMOS Memory Arrays", IBM T.D.B., vol. 30, No. 2, Jul. 1987, pp. 664-666.

Affiliated with

Also associated with

Rating

Complementary output, high-density CMOS decoder/driver circuit f does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Complementary output, high-density CMOS decoder/driver circuit f, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary output, high-density CMOS decoder/driver circuit f will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-815526