Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-26
2003-02-04
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06515907
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an electrically rewritable non-volatile memory circuit. More specifically, the present invention is directed to a FLOTOX type (Floating-gate Tunneling Oxide) non-volatile memory circuit capable of shortening data rewriting time.
2. Description of the Related Art
One conventional FLOTOX type non-volatile memory is represented in FIG.
5
. In this FLOTOX type non-volatile memory, a terminal voltage across one real memory element
6
, and a terminal voltage across one dummy memory element
12
, which are connected to current load circuits, are compared with each other by a sense amplifier circuit
1
constructed of a voltage comparing circuit in order to judge as to whether data is equal to “0” or “1.”The sense amplifier circuit
1
receives a bias voltage SABIAS input to transistors
3
and
9
. An output signal of the sense amplifier SAOUT represents the comparison result. Transistors
6
,
12
receive bias signals CGBIAS and FGBIAS, respectively; whereas transistors
7
,
12
receive bias signals RD and SAEN, respectively. The current load circuits are constituted by NMOS transistors
2
and
3
, and NMOS transistors
8
and
9
, respectively.
Referring to the drawing, operations of this conventional non-volatile memory circuit will be described.
The real memory element
6
may have two values, namely, an enhancement state and a depletion state. A voltage of “IN+” is changed, depending upon the state of this real memory element
6
, and this “IN+” corresponds to an input node of the sense amplifier circuit
1
provided on the side of the real memory cell
6
. As a result, this voltage is compared with a reference voltage of “IN−” corresponding to another input node of this sense amplifier circuit
1
provided on the side of the dummy cell in order to judge as to whether data is equal to “0” or “1.”
At this time, a bias voltage (CGBIAS) is applied to a control gate of the real memory cell
6
. This bias voltage is substantially equal to an intermediate value defined between a threshold voltage when the real memory cell
6
is brought into an enhancement state, and another threshold voltage when the real memory cell
6
is brought into a depletion state.
The real memory element
6
selects a desirable 1 bit from a large number of memory cells existing in an memory array by operating both a column selector transistor
4
with a signal COLSEL and a row selector transistor
5
with a signal ROWSEL. In this case, when a serial input/output type non-volatile memory is employed, a bit selecting transistor may be further additionally employed. Generally speaking, in the case where an array is constituted by using a FLOTOX type non-volatile memory, two elements made of one pair of both the real memory element
6
and the row selector transistor
5
(namely, select gate transistor) may function as a 1-bit memory cell.
In the case where data is written into an FLOTOX type memory cell, when the memory cell is brought into an enhancement state, a control gate is set to a high voltage of 18 V to 22 V and also a drain is set to 0 V, so that electrons are injected into a floating gate via a tunnel oxide film having a thickness of on the order of 80 to 120 angstrom by utilizing an FN (Fowler-Nordheim) tunnel current. In order to bring the memory cell to a depletion state, the control gate is set to 0 V and the drain is set to [such] a high voltage such as 18 to 22 V, so that holes are injected into the floating gate by similarly utilizing an FN tunnel current.
An FN tunnel current starts to flow when an electric field of approximately 10 to 12 V is applied to a tunnel oxide film, while this flow of the FN tunnel current is determined depending upon a thickness of the tunnel oxide film.
At this time, in order to bring the memory cell to the depletion state, once this memory cell is brought into the enhancement state, and thereafter, a high voltage must be applied to the drain in order to avoid a leak occurred between the source and the drain during data writing operation. When data is written into a memory cell, since no clear definition is made that what data has been previously written into this memory cell, as a write sequence, a so-called “erase cycle” is executed. That is, at the beginning, the memory cell must be brought into the enhancement state without any exception. Thereafter, a high voltage is applied only to such a drain of a memory cell which will be brought into the depletion state in a so-called “write cycle.”
Generally speaking, when data are successively rewritten into an FLOTOX type non-volatile memory, a film quality of a tunnel oxide film thereof is deteriorated, a difference between a threshold value of an enhancement state and a threshold value of a depletion state is gradually decreased. Finally, this tunnel oxide film is broken, so that data cannot be written and read. Also, in such a memory cell into which data has been written, electron charges which have been stored in a floating gate are gradually extracted. In particular, under high temperature condition, these electron charges apparently disappear. As a result, a difference between a threshold voltage of an enhancement state and a threshold voltage of a depletion state becomes small, and data cannot be finally read by a sense amplifier. As a consequence, when data is written into the non-volatile memory, the data should be deeply written in such a manner that the difference between the threshold voltages of both the enhancement state and the depletion state may become sufficiently large by considering these conditions. At this time, both a data rewritable time and a data writing depth may depend upon a high voltage which is applied when data is written. When the data write voltage is increased, the data write depth becomes sufficiently deep, and also margin used to be read by the sense amplifier is increased. However, stress given to the tunnel oxide film is increased, and a total data rewritable time is decreased. To the contrary, when the data write voltage is decreased, since stress applied to the tunnel oxide film is reduced, a total data rewritable time is increased. However, the data write depth.becomes shallow. In other words, since a difference between the threshold voltages of the depletion state and the enhancement state is small, such a difference between an input voltage entered into a sense amplifier provided on the side of a real memory cell, and another input voltage entered into another sense amplifier provided on the side of a dummy cell is decreased. As a result, a data reading speed is delayed. In the worst case, the data cannot be read out from the non-volatile memory.
Since there is such a trade-off relationship between the total data rewritable time and the data write depth, the conventional FLOTOX type non-volatile memory owns such a limitation. That is, the high voltage used to write the data is selected to be 18 V to 22 V, and a total data rewritable time is limited to 100,000 times up to 1,000,000 times.
Also, since the.conventional non-volatile memory requires two sequences constructed of an erase cycle and a write cycle in order to write data into this non-volatile memory, data writing time is prolonged.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-described problems, and therefore, has an object to provide a non-volatile memory circuit. That is, a non-volatile memory circuit according to a first aspect of the present invention is featured by such a non-volatile memory circuit using FLOTOX type electrically rewritable non-volatile memory elements comprising: a first data line to which a drain electrode of a first non-volatile storage element is connected via at least a first single e selection transistor; and a second data line to which a drain of a second non-volatile storage element is connected via at least a second single selection transistor; in which: a gate electrode of the first non-volatile storage element is connected to
Adams & Wilks
Phan Trong
Seiko Instruments Inc.
LandOfFree
Complementary non-volatile memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Complementary non-volatile memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary non-volatile memory circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3179829