Complementary non-volatile memory cell

Details Complementary non-volatile memory cell Complementary non-volatile memory cell

2002-10-28

2004-09-07

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185170, C365S158000, C365S185290

Reexamination Certificate

active

06788576

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuits, and in particular to complementary metal-oxide-silicon (CMOS) integrated circuits that include non-volatile memory (NVM) devices, such as arrays of flash memory or electrically erasable programmable read only memory cells.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable read only memories (EEPROMs) and flash erasable and programmable read only memories (flash EPROMs) are two types of non-volatile memory (NVM) devices that can be embedded into an integrated circuit (IC) to provide non-volatile data storage for the IC circuitry. ICs including embedded NVM devices have an advantage over other ICs in that certain data (e.g., configuration settings or security information) can be retained in the IC even if power is disconnected.
Embedded EEPROM and flash EPROM cells (hereafter collectively referred to as an EEPROM cell for brevity) typically comprise a sort of modified field-effect transistor (FET) that includes an electrically isolated floating gate (e.g., polycrystalline silicon or oxide-nitride-oxide (ONO)) for controlling conduction between source and drain regions of the EEPROM cell. A gate dielectric (bottom oxide) is formed between the floating gate and an underlying channel region between the source and drain regions. A control gate is provided adjacent to (e.g., above) the floating gate, and is separated from the floating gate by an inter-gate dielectric (top oxide).
The data value stored by an EEPROM cell is determined by the amount of charge stored in the floating gate, which is controlled during program and erase operations by applying predetermined voltages across the floating gate. For example, during a program (write) operation, a net negative charge is transferred to and stored by the floating gate using a technique such as hot electron injection or Fowler-Nordheim (FN) tunneling. In this programmed state, the negative charge stored by the floating gate prevents current flow between the source and drain regions of the memory cell when the control gate is asserted (i.e., pulled high). Conversely, an erase operation transfers a net negative charge from the floating gate using, for example, FN tunneling. In the erased state, the neutral charge stored by the floating gate permits current flow between the source and drain regions of the memory cell when the control gate is asserted.
One of the limitations associated with incorporating “embedded” EEPROM cells into ICs fabricated using conventional complementary metal-oxide-silicon (CMOS) techniques is that EEPROM cells typically require special processing steps that are not part of “standard” CMOS fabrication processes. For example, EEPROM cells employing FN tunneling typically require additional “deep” n-type well (deep n-well) structures to generate high fields in the bottom oxide of the EEPROM cells, which are necessary to facilitate the FN tunneling process but are typically not part of “standard” CMOS processes. Further, the high fields are generated by applying a positive voltage to the deep n-well, and applying a negative voltage to the control gate of the EEPROM cell, thereby producing a relatively high voltage potential across the oxides surrounding the floating gate (i.e., compared to that of “normal” FETs produced on the IC device). This high voltage potential produces a need for special high voltage oxides for the EEPROM cells, which are also typically not part of “standard” CMOS processes. As a result, a “standard” CMOS process must be modified to include additional masks and process steps to facilitate the formation of the EEPROM cells, which increases the manufacturing costs of the ICs produced by the modified CMOS process.
Another limitation associated with incorporating “embedded” EEPROM cells into ICs is the large amount of chip area required for controlling EEPROM operations. As mentioned above, EEPROMs require relatively high voltages to perform program and erase operations using FN or hot electron injection techniques. In the case of Channel Hot Electron (CHE) programming, large currents flow in the EEPROM channels. To generate these high voltages and to maintain these high currents, charge pumps are typically provided adjacent the EEPROM cells that convert relatively low system voltages into the high voltages needed during program and erase according to known techniques. In addition to the chip area required for these charge pumps, conventional embedded EEPROM cells typically require additional control circuitry for monitoring the amount of charge stored on the floating gate during erase operations in order to prevent an over-erase condition. That is, if too large of a net positive charge is stored on the floating gate due to over-erasure, then the EEPROM cell remains turned on even when the control gate is de-asserted. The control circuitry performs an algorithm in conjunction with sensing circuitry that applies the erasing voltage for a short period, measures the charge stored on the floating gate after each period, and terminates the erasing operation when the desired neutral charge is achieved. The total chip area required for is control circuitry and the charge pump, along with other circuitry needed to operate the EEPROM cells, significantly increases the overall IC device size, thereby making IC devices with embedded EEPROM cells relatively expensive.
What is needed is a low cost NVM embedded memory cell that is easily integrated into standard CMOS process. In particular, what is needed is an NVM embedded memory cell that exhibits low power consumption (low voltages and currents) in all operating regimes (program, erase, read), is operated using simple program/erase algorithms, and requires a small area periphery (i.e., for sensing stored data values, and charge pumps needed to generate program/erase voltages).
SUMMARY OF THE INVENTION
The present invention is directed to a complementary non-volatile memory (CNVM) cell including a p-channel transistor and an n-channel transistor that share both a floating gate structure and a control gate structure (i.e., a floating gate structure extends over channel regions of both the p-channel and n-channel transistors). In addition, the drain terminal of the n-channel transistor is connected to the drain terminal of the p-channel transistor, and the CNVM cell also includes a select transistor connecting the drains of the p-channel and n-channel transistors to a read bit line.
According to an aspect of the present invention, by using shared floating gate structure and a shared control gate to control the operation of the p-channel and n-channel transistors, the CNVM cell facilitates band-to-band tunneling (BBT) during both program and erase operations. BBT facilitates both low current and relatively low voltage program/erase operations that can be facilitated using standard CMOS fabrication processes. In one embodiment, the CVNM cell is programmed by applying a relatively low negative voltage (e.g., −6 V) to the source of the p-channel transistor, and a relatively low positive voltage (e.g., +6 V) to the control gate structure (the source of the n-channel transistor is open (floating), and the n-well in which the p-channel transistor is formed is grounded). Under these conditions, BBT electrons generated in the source of the p-channel transistor are injected into the floating gate structure through the intervening gate oxide, thereby increasing the net negative charge stored in the floating gate. Conversely, the CNVM cell is erased by applying a relatively low positive voltage (e.g., +6 V) to the source of the n-channel transistor and a relatively low negative voltage (e.g., −6 V) to the control gate structure (both the source of the n-channel transistor and the n-well in which the p-channel transistor is formed are open (floating)). Under these conditions, BBT holes generated in the source of the n-channel transistor flow into the floating gate structure (or back tunneling electrons pass from the floating gate into the source of the n-channel tr

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