Patent
1978-03-24
1979-09-11
Wojciechowicz, Edward J.
357 23, 357 41, 357 48, H01L 2702
Patent
active
041677471
ABSTRACT:
A CMOS device comprising an N type semiconductor substrate, a P type well region diffused in the substrate, an n-channel MOS transistor formed in the P type well region, and a p-channel MOS transistor formed in the N type semiconductor substrate, and a method for manufacturing the CMOS device. In case the CMOS device serves as a CMOS inverter, the source region of the p-channel MOS transistor, the semiconductor substrate and the well layer constitute a parasitic PNP type bipolar transistor, and the source region of the n-channel MOS transistor, the well layer and the semiconductor substrate constitute a parasitic NPN type bipolar transistor. The product of the current amplification factor .beta..sub.1 of the PNP type bipolar transistor and the current amplification factor .beta..sub.2 of the NPN type bipolar transistor is smaller than 1.
REFERENCES:
patent: 3934159 (1976-01-01), Nomiya et al.
patent: 3955210 (1976-05-01), Bhatia et al.
RCA-Tech. Notes-No. 876-Feb. 1971-Dennehy.
Satou Kazuo
Ueno Mitsuhiko
Tokyo Shibaura Electric Co. Ltd.
Wojciechowicz Edward J.
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