1977-11-16
1979-04-10
Wojciechowicz, Edward J.
357 44, 357 46, 357 23, H01L 2702
Patent
active
041491769
ABSTRACT:
A CMOS device comprising an N type semiconductor substrate, a P type well layer diffused in the substrate, a p-channel MOS transistor formed in the N type semiconductor substrate an n-channel MOS transistor formed in the P type well layer. A distance from an edge of a contact hole formed in the surface of a contact region of the p-channel MOS transistor to the P well layer is so chosen to suppress an operation of a parasitic bipolar transistor whose base is formed of the substrate.
REFERENCES:
patent: 3934159 (1976-01-01), Nomiya et al.
patent: 3955210 (1976-05-01), Bhatia et al.
Dennehy, RCA, Tech. Notes, No. 876, Feb. 12, 1971.
Satou Kazuo
Ueno Mitsuhiko
Tokyo Shibaura Electric Co. Ltd.
Wojciechowicz Edward J.
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