1978-06-20
1979-05-01
Wojciechowicz, Edward J.
357 23, 357, H01L 2702
Patent
active
041527178
ABSTRACT:
A CMOS FET device having a P well layer diffused in an N type semiconductor substrate, a P channel MOS transistor formed on the N type semiconductor substrate, and an N channel MOS transistor provided in the P well layer, wherein the source of the P channel MOS transistor is made to have the same potential as the N type semiconductor substrate and for the source of the N channel MOS transistor is made to have the same potential as the P well layer, thereby suppressing the operation of a parasitic bipolar transistor whose base is constituted by the N type semiconductor substrate and/or a parasitic bipolar transistor whose base is formed of the P well layer.
REFERENCES:
patent: 3641511 (1972-02-01), Cricchi et al.
patent: 3967295 (1976-06-01), Stewart
Satou Kazuo
Ueno Mitsuhiko
Tokyo Shibaura Electric Co. Ltd.
Wojciechowicz Edward J.
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