Complementary MOS transistors without an isolation region

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357 23, 357 89, H01L 2702, H01L 2978

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042310555

ABSTRACT:
A first semiconductor region of P.sup.- type is formed in a semiconductor substrate of N.sup.- types. The N.sup.- region adjacent to the first semiconductor region is a second semiconductor region. A third semiconductor region of N.sup.+ type and a fourth semiconductor region of P.sup.+ type are formed on the first and second semiconductor regions, respectively. Between the first semiconductor region and fourth semiconductor region is formed a first channel region which includes a subregion of P.sup.- type and a fifth semiconductor region of N types. Between the second semiconductor region and third semiconductor region is formed a second channel region which includes a subregion of N.sup.- type and a sixth semiconductor region of P type. The fourth semiconductor region, the subregion of the first channel region and the sixth semiconductor region are used for a P-channel MOS transistor. The third semiconductor region, the subregion of the second channel region and the fifth semiconductor region are used for an N-channel MOS transistor.

REFERENCES:
patent: 3840888 (1974-10-01), Gaensslen et al.
patent: 3893155 (1975-07-01), Ogiue
patent: 4131907 (1978-12-01), Ouyang
patent: 4152717 (1979-05-01), Satou et al.
IPRI "Lambda Diodes Utilizing an Enhancement-Depletion C MOS/SOS Process" IEEE Trans. Electron Devices vol. ED-24 pp. 7-12.

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