Patent
1985-08-14
1987-06-02
Munson, Gene M.
357 234, 357 49, 357 55, 357 56, H01L 2702, H01L 2978, H01L 2712, H01L 2906
Patent
active
046707689
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
The present invention relates to semiconductor integrated circuits, and particularly to semiconductor integrated circuits (C-MOS circuits: complementary MOS circuits) having a p-channel FET (field-effect transistor) and an n-channel FET.
2. Background Art
A semiconductor integrated circuit having an n-channel FET and a p-channel FET can be represented by a CMOS integrated circuit employing insulated gate-type field-effect transistors (MOS transistors) as FET's.
The CMOS integrated circuit is fundamentally based upon an inverter circuit which consists of an n-channel MOS transistor 1 and a p-channel MOS transistor 2 as shown in FIG. 1, wherein reference numeral 3 denotes an input terminal, 4 denotes an output terminal, 5 denotes a Vss terminal, and 6 denotes a Vcc terminal.
Referring to FIG. 2, the inverter circuit of FIG. 1 consists of the n-channel MOS transistor 1 and the p-channel MOS transistor 2 formed in a p-type well region 9 and an n-type well region 11, that are formed in a silicon substrate 10. Here, though both the p-type well region and the n-type well region are formed, the silicon substrate 10 may be utilized to serve as either one of them, so that only either one well region needs be formed. In FIG. 2, the n-type well region and the p-type well region are formed in the n.sup.- -type well region. In FIG. 2, furthermore, reference numeral 7 denotes n.sup.+ -type regions, 8 denotes p.sup.+ -type regions, 12 denotes field insulators for device isolation, 13 denotes gate electrodes, 14 denotes insulators, 90 denotes p-type regions, and 91 denotes n-type regions.
The CMOS structure has heretofore been formed in plane as shown in FIG. 2. That is, a wide field oxide film 12 must be formed in order to electrically isolate the n-channel MOS transistor 1 from the p-channel MOS transistor 2. Further, the p-type well region and the n-type well region must be separated from each other when there arises a problem of breakdown voltage therebetween due to their high impurity concentrations. In either case, the CMOS device is prevented from being integrated to a high degree. In the integrated circuit having a 2 .mu.m-long gate level, for instance, the field oxide film 12 must have a width of about 10 .mu.m to isolate the wells. Even in the integrated circuit having a 1 .mu.m-long gate level, the field oxide film must have a width of about 5 .mu.m.
The above-mentioned known C-MOS technique has been disclosed in Japanese Patent Publication Nos. 44555/1974 and 33229/1974.
DISCLOSURE OF INVENTION
Further, so-called vertical MOSFET's and V-grooved MOSFET's having resembling appearance or construction have been disclosed in Japanese Patent Publication Nos. 26823/1968 and 456/1968.
DISCLOSURE OF THE INVENTION
The object of the present invention is to provide well-to-well isolation of a high-density structure that had been one of the greatest obstacles against realizing the semiconductor integrated circuits of the CMOS construction in a highly integrated form.
According to the present invention, the skeltal structure resides in that a p-well (n-channel forming region) and an n-well (p-channel forming region) are formed being opposed to each other with a thin insulating region interposed therebetween, in order to realize a CMOS integrated circuit in a highly integrated form.
According to the present invention, an n-channel MOS transistor is isolated from a p-channel MOS transistor by a thin insulating region, making it possible to obtain the CMOS integrated circuit in a highly integrated form and to very efficiently prevent the occurrence of a latch-up that is detrimental to the CMOS construction. Moreover, it is allowed to form transistors having a particularly large transfer conductance in very small regions.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a circuit diagram of a conventional CMOS inverter;
FIG. 2 is a section view showing the structure of a conventional CMOS inverter;
FIGS. 3, 4, 5 and 6 are section views showing the manufacturing steps according to an embodiment of
REFERENCES:
patent: 3893155 (1975-07-01), Ogiue
patent: 4131907 (1978-12-01), Ouyang
patent: 4229756 (1980-10-01), Sato et al.
Kimura Shin'ichiro
Ohkura Makoto
Sunami Hideo
Hitachi , Ltd.
Munson Gene M.
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