Patent
1985-07-30
1987-04-21
Wojciechowicz, Edward J.
357 231, 357 41, 357 45, H01L 2702
Patent
active
046600671
ABSTRACT:
The complementary MOS integrated circuit has a first channel MOS FET in a substrate of one conductivity type and a second channel MOS FET in a well region of the other conductivity type, and further comprises a first high impurity region of the one conductivity type formed in the substrate so as to surround the first channel MOS FET, a second high inpurity region of the other conductivity type formed in the well region so as to surround the second channel MOS FET, a first insulator film covering the first and second high impurity regions and having a plurality of first holes, a first wiring layer formed on the first insulator film with connections with the first high impurity region through the first holes, so as to surround the first channel MOS FET, a second wiring layer formed on the first insulator film with connections with the second high impurity region through the second holes, so as to surround the second channel MOS FET, a second insulator film covering the first and second wiring layers and having a plurality of second holes, a third wiring layer formed on the second insulator film, connected with the first wiring layer through the second holes and supplied with a first power potential, and a fourth wiring layer formed on the second insulator film, connected with the second wiring layer through the second holes and supplied with a second power potential.
REFERENCES:
patent: 4062039 (1977-12-01), Nishimura
patent: 4167747 (1979-09-01), Satou
patent: 4270262 (1981-06-01), Hori et al.
NEC Corporation
Wojciechowicz Edward J.
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