Complementary MOS circuit having decreased parasitic capacitance

Details Complementary MOS circuit having decreased parasitic capacitance Complementary MOS circuit having decreased parasitic capacitance

1984-01-23

1989-06-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, 3072962, H03K 1714

Patent

active

048374601

ABSTRACT:
The substrate voltages V.sub.1 and V.sub.2 of NMOS and PMOS transistors, respectively, which constitute a CMOS circuit and the source voltages V.sub.3 and V.sub.4 of these transistors have the following relationship:

REFERENCES:
patent: 3855549 (1974-12-01), Huener et al.
patent: 4006491 (1977-02-01), Alaspa et al.
patent: 4039869 (1977-08-01), Goldman et al.
patent: 4122360 (1978-10-01), Kawagai et al.
patent: 4209713 (1980-06-01), Satou et al.
patent: 4305009 (1981-12-01), Miyagawa et al.
patent: 4585955 (1986-04-01), Uchida
"Comment Se Premunir Du Latch-Up Dans Les Curcuits Integres CMOS", Electronique Industrielle, No. 18/15-5-81.

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