Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...
Reexamination Certificate
2001-07-30
2003-11-25
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
C257S544000, C257S549000, C257S552000, C257S593000
Reexamination Certificate
active
06653708
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of transistors, and more particularly, this invention relates to junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor devices.
BACKGROUND OF THE INVENTION
In a standard junction isolated Complementary Metal Oxide Semiconductor transistor device using a P-substrate and N-buried layer, Single Event Effects performance is degraded because of parasitic vertical NPN bipolar action in the N-channel MOS device. As is well known to those skilled in the art, one standard layout places both NMOS and PMOS transistor devices over a common N-conductivity buried layer, which is biased to a positive voltage, such as five volts, and acts as the electrical contact to the PMOS N-well. The N-conductivity buried layer is common with the device next to it and are both tied to the supply voltage. The source and the body are tied together respective to the body of the P-channel.
For the NMOS, the N-conductivity buried layer acts as a collector of a parasitic, vertical, bipolar NPN transistor. The P-well is the base region and the N+ source/drains are emitters. For this parasitic NPN bipolar transistor, the collector is at +5 volts and the P-well is tied to the source back through a body contact.
The drain, depending on the state of the device, is at a logic 0 state, i.e., 0 volts. In some space applications, e.g., satellite circuits, where heavy ions bombard the circuit, a Single Event Effect (SEE) performance can be a problem. For example, heavy ions, such as an iron ion, can pass through a space craft or satellite into a semiconductor integrated circuit, passing through the NMOS transistor device as described before, and thus, through the parasitic, vertical NPN transistor to create a charged ion track. As a result, the device dumps a charge into the base node and the series resistance back to the body contact is high enough to internally forward bias the base/emitter junction, thus, turning on this parasitic NPN transistor. Whatever charge was dumped into the base is beta multiplied because it is biased in the active region.
The emitter acting as the drain of the MOS device is grounded. The collector is at +5 volts and the base has been pumped to where it is forward biased by dumping that charge into the P-well. Thus, a large dump of current is formed into the drain and the MOS device may not be sized sufficiently large enough to handle the amount of current. As a result, the device is driven out of the logic zero state and driven into an error state to a logic 1 state. This creates a logic fault that could propagate when the circuit is tied into a toggle input of a flip flop. This would clock the flip flop, creating potentially adverse consequences.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to form a CMOS transistor device of the type as described that has reduced Single Event Effect performance.
The present invention is advantageous and provides a junction isolated CMOS transistor device where the N-conductivity buried layer under the NMOS transistor device is separated from the N-conductivity buried layer under the PMOS transistor device. The layer under the NMOS is now tied to ground. As a result, the parasitic bipolar transistor will not be in the active region any more. It is possible to have a charge dumped, and still forward bias the base emitter, but without beta multiplication. This results from the N-buried layer collector, now at zero volts, as not being biased for current to flow.
In accordance with the present invention, a Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite the first conductivity type. First and second well regions of respective first and second conductivity are formed at respective first and second buried layers. A NMOS transistor and PMOS transistor are formed at respective first and second well regions. In one aspect of the present invention, the buried layer having the NMOS transistor is grounded and the buried layer having the PMOS transistor is biased at a positive signal voltage to improve Single Events Effects occurrence. The two transistors are sufficiently spaced to obtain proper breakdown voltage.
In another aspect of the present invention, the conductivity of all the layers can be reversed. This results in a CMOS process that has an N-type substrate and a P-buried layer. The P-buried layer would be tied to the -supply voltage, typically 0V, as it is in electrical contact with the NMOS body which must be tied to 0V for proper circuit operation. The parasitic device of concern now becomes a parasitic vertical PNP where the PNP emitter is formed by the PMOS drain, the PNP base is formed by the PMOS body and the PNP collector is the P-buried layer. This PMOS device could be used as the pull-up device in a logic gate, for example, in the logic 1 state. If a heavy ion now passes through the above described layers, the PNP can be turned on pulling beta multiplied current out of the PMOS drain. This could result in the logic 1 state being corrupted. The analogous solution in this case is to separate the P-buried layers and tie the buried layer under the PMOS devices to +V such that the parasitic PNP is not biased for current multiplication.
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Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Fahmy Wael
Intersil America's Inc.
Rao Shrinivas H
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