Complementary metal-oxide semiconductor transistor logic using s

Details Complementary metal-oxide semiconductor transistor logic using s Complementary metal-oxide semiconductor transistor logic using s

1994-05-20

1996-07-09

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

257190, 257192, 257616, H01L 2906

Patent

active

055347134

ABSTRACT:
A method and a layered planar heterostructure comprising one of or both n and p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate wherein one layer is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby n channel field effect transistors may be formed with a silicon or silicon germanium layer under tension and p-channel field effect transistors may be formed with a silicon germanium layer under compression. The plurality of layers may be common to both subsequently formed p and n-channel field effect transistors which may be interconnected to form CMOS circuits. The invention overcomes the problem of forming separate and different layered structures for p and n-channel field effect transistors for CMOS circuitry on ULSI chips.

REFERENCES:
patent: 4710788 (1987-12-01), Dambkes et al.
patent: 5006912 (1991-04-01), Smith et al.
patent: 5019882 (1991-05-01), Solomon et al.
patent: 5155571 (1992-10-01), Wang et al.
patent: 5227644 (1993-07-01), Ueno
patent: 5241197 (1993-08-01), Murakami et al.
"Si/SiGe Heterostructure MOS Devices with Step-Graded Bandgap Profile of the SiGe Channel," IBM Technical Disclosure Bulletin, vol. 36, No. 03, Mar. 1993, pp. 127-129.
Ismail et al., "High-Performance Si/SiGe n-Type Modulation-Doped Transistors," IEEE Electron Device Letters, vol. 14, No. 7, Jul. 1993, pp. 348-350.

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