Complementary metal oxide semiconductor integrated circuit with

Details Complementary metal oxide semiconductor integrated circuit with Complementary metal oxide semiconductor integrated circuit with

1987-05-04

1988-09-20

James, Andrew J.

357 45, 357 236, 357 44, H01L 2702

Patent

active

047729309

ABSTRACT:
A power supply voltage to be applied to a metallic connection 36a is supplied through an n.sup.+ diffusion region 34a, an N type well 22, an n.sup.+ diffusion region 34c and a metallic connection 36C to a p.sup.+ diffusion region 23b serving as a power supply line. An n.sup.+ diffusion region 73 serving as a ground line is grounded through a metallic connection 76c, a p.sup.+ diffusion region 74c, a P type well 72, a p.sup.+ diffusion region 74b and a metallic connection 76b.

REFERENCES:
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patent: 4327368 (1982-04-01), Uchioa
patent: 4660067 (1987-04-01), Ebina
Chen, "Latch-Up Elimination in High Density DMOS", 1983 VLSI Symposium Digest, pp. 54-55.

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