Complementary metal-oxide semiconductor device

Details Complementary metal-oxide semiconductor device Complementary metal-oxide semiconductor device

2001-08-30

2002-06-11

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S206000, C257S357000, C257S500000

Reexamination Certificate

active

06403992

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a complementary metal-oxide semiconductor (CMOS) device, and more particularly, to a CMOS device using circuit conversion to eliminate body effect and to obtain multiple voltage levels.
2. Description of the Related Art
In the prior art, CMOS devices, for example, CMOS devices having N-type substrates are fabricated by a twin-well high voltage fabrication process. As shown in
FIG. 1
, the N-type substrate of the high voltage PMOS
10
and N-type substrate of the low voltage PMOS
12
communicate with each other via the underlying N-type substrate. Consequently, the voltage level of the substrate (B
4
) of the low PMOS
12
is equal to that of the substrate (B
2
) of the high voltage PMOS
10
. A serious body effect thus occurs to the low voltage PMOS
12
. As the substrate voltage level of the low voltage PMOS
12
increases, the reverse bias from the source (S
4
) of the low voltage PMOS
12
to the substrate (B
4
) is increased to cause an increase of the threshold voltage of the low voltage PMOS
12
. When the input operation voltage is a low voltage, the low voltage PMOS
12
cannot operate normally.
FIG. 2
shows a CMOS device with a P-type substrate. Since the P-wells of the high voltage NMOS
24
and the low voltage NMOS
26
conduct via the underlying P-type substrate, the substrate (B
3
and B
1
) voltage levels of the low voltage NMOS
26
and the high voltage NMOS
24
are the same. A serious body effect is caused. As the substrate (B
3
) voltage level of the low voltage NMOS
26
decreases, the reverse bias from the source (S
3
) of the low voltage NMOS
26
to the substrate (B
3
) increases to cause an increase in threshold voltage of the low voltage NMOS
26
. When the input voltage is a high voltage, the low voltage NMOS
26
cannot function properly.
A conventional method for a CMOS device to obtain multiple voltage levels with the elimination of substrate effect is introduced here. In
FIG. 3
, a CMOS device with an N-type substrate is illustrated. An additional P-well
382
is added in the low voltage CMOS area of the CMOS device, so that the problem caused by conductance between the N-wells is resolved. The body effect is thus eliminated and the low voltage PMOS
32
can function normally.
FIG. 4
illustrates a CMOS device with a P-type substrate. Similarly, an additional N-well
484
is added in the low voltage CMOS area of the CMOS device so that the problem caused by communication between the P-wells is resolved. The body effect is thus eliminated; the low voltage NMOS
46
can operate normally.
The prior art has the following drawbacks:
1. Since an additional P-well
382
(N-well
484
) is required for the CMOS with the N-type (P-type) substrate to overcome the problem of the communication between the N-wells (P-well), the difficulty in fabrication is increased.
2. As the fabrication becomes more complex, the fabrication cost is raised.
SUMMARY OF THE INVENTION
The invention provides a CMOS device applying circuit conversion to eliminate the body effect to obtain multiple voltage levels. Since the circuit conversion is applied to eliminate the body effect, the fabrication process only requires a typical twin-well high voltage process without increasing the fabrication cost.
The invention provides a method to eliminate the body effect to obtain multiple voltage levels of a CMOS device. A typical twin-well fabrication process is used. The CMOS device comprises a high voltage CMOS and a low voltage CMOS. The high voltage CMOS further includes a high voltage PMOS and a high voltage NMOS. The high voltage PMOS has a source and a substrate connected to a positive voltage source, and an N-well. The high voltage NMOS has a source and a substrate connected to a negative voltage source, and a P-well. The low voltage CMOS further comprises a low voltage PMOS and a low voltage NMOS. The low voltage PMOS has a substrate, a source and a substrate connected to a positive voltage source lower than that of the high voltage PMOS. The low voltage NMOS has a substrate, a source and a substrate connected to a positive voltage source lower than that of the high voltage NMOS. A substrate such as a common substrate for the high voltage CMOS and the low voltage CMOS is further included in the CMOS device. The substrate includes a P-type substrate or an N-type substrate. The CMOS device further comprises a circuit converter to raise the voltage level of the low voltage PMOS in the low voltage CMOS up to the operation voltage of the high voltage PMOS in the high voltage CMOS. Alternatively, the operation voltage level of the low voltage NMOS in the low voltage CMOS is reduced to the operation voltage of the high voltage NMOS in the high voltage CMOS.
In one embodiment of the invention, if the CMOS device has an N-type substrate, the source operation voltage of the low voltage PMOS in the low voltage CMOS is raised up to the source operation voltage of the high voltage PMOS in the high voltage CMOS via a first level shifter in the circuit converter. The voltage via the first level shifter is called the first level shifted output voltage. Secondly, the source operation voltage of the low voltage NMOS in the low voltage CMOS, is raised to a voltage with the original input voltage of the low voltage CMOS less than the first level shifter output voltage (that is, a difference between the input maximum voltage and the input minimum voltage). The output voltage of the charge pump is called the charge pump output voltage. Via the voltage clamp circuit of the circuit converter, the first shifter output voltage is referred as the maximum voltage level of the input voltage for the low voltage CMOS, and the charge pump output voltage is the minimum level of the input voltage for the low voltage CMOS. When the input voltage reaches the maximum level, the low voltage NMOS in the low voltage CMOS conducts. Meanwhile, the minimum levels of the output voltage and the input voltage are the same. When the input voltage reaches the minimum level, the low voltage PMOS in the low voltage CMOS conducts. Meanwhile, the low voltage PMOS in the low voltage CMOS conducts and the maximum levels of the output voltage and input voltage are the same. Via the second level shifter in the circuit converter, the maximum level and the minimum level of the output voltage are reduced to the original maximum and minimum levels of the output voltage for the low CMOS.
In another embodiment of the invention, the CMOS device has a P-type substrate. The source operation voltage of the low voltage NMOS in the low voltage CMOS is raised up to the source operation voltage of the high voltage NMOS in the high voltage CMOS via a first level shifter in the circuit converter. The voltage via the first level shifter is called the first level shifted output voltage. Secondly, the source operation voltage of the low voltage PMOS in the low voltage CMOS, is raised to a voltage with the original input voltage of the low voltage CMOS less than the first level shifter output voltage (that is, a difference between the input maximum voltage and the input minimum voltage). The output voltage of the charge pump is called the charge pump output voltage. Via the voltage clamp circuit of the circuit converter, the first shifter output voltage is referred as the minimum voltage level of the input voltage for the low voltage CMOS, and the charge pump output voltage is the maximum level of the input voltage for the low voltage CMOS. When the input voltage reaches the maximum level, the low voltage NMOS in the low voltage CMOS conducts. Meanwhile, the minimum levels of the output voltage and the input voltage are the same. When the input voltage reaches the minimum level, the low voltage PMOS in the low voltage CMOS conducts, and the maximum levels of the output voltage and input voltage are the same. Via the second level shifter in the circuit converter the maximum level and the minimum level of the output voltage are reduced to the original maximum and m

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