Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
2001-06-28
2002-05-07
Lee, Benny (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S255000
Reexamination Certificate
active
06384685
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an amplifier circuit, and especially to a complementary metal-oxide semiconductor (CMOS) class AB amplifier.
2. Description of Related Art
FIG. 4
shows a conventional class AB amplifier, which includes an input-stage formed by a differential amplifier
41
, and an output stage formed by an class AB amplifier
42
, so as to perform a differential operation on an input signal, and amplify and drive the same for output.
The AB class amplifier can be analyzed as follows: The class AB amplifier
42
with a loading capacitor C
L
has an open loop voltage gain, from node A to node O, expressed as:
A
AO
(
s
)
=
V
O
(
s
)
V
A
(
s
)
=
(
gm
2
+
gm
1
gm
6
r
B
sC
B
r
B
+
1
)
(
r
O
sC
L
r
O
+
1
)
,
(
1
)
where r
B
=r
ds4
//r
ds5
is a DC resistance on node B; r
o
=r
ds2
//r
ds6
is an DC output resistance of the output stage; gm
j
represents transfer-conductance of a MOS transistor M
j
, j=1,2,3 . . . ; C
B
=C
DB4
+C
DB5
+C
GD4
+C
GD5
+gm
6
r
O
C
GD6
is a parasitic capacitance of the output MOS transistor M
6
and the current mirror amplifier consisting of MOS transistors M
4
and M
5
.
When the class AB amplifier employs in an operational amplifier with a compensation capacitor C
F
, its output impedance with a loading capacitor C
L
becomes:
y
O
(
s
)
=
1
/
z
O
(
s
)
=
sC
F
r
A
+
1
r
A
+
sC
F
r
A
sC
F
r
A
+
1
(
gm
2
+
gm
1
gm
6
r
B
sC
B
r
B
+
1
)
+
1
r
O
+
sC
L
,
(
2
)
where r
A
is a DC resistance on node point A, i.e., an output resistance of the differential amplifier. If &ohgr;>>1/(r
A
C
F
), and
gm
2
⪢
1
r
A
+
1
r
O
,
we have
y
OH
(
s
)
=
1
/
z
OH
(
s
)
=
gm
2
+
gm
1
gm
6
r
B
1
sC
B
r
B
+
1
+
sC
L
,
(
3
)
herein, the term
gm
1
gm
6
r
B
1
sC
B
r
B
+
1
represents a gyrated output inductor,
where,
L
OEQ
≈C
B
/(
gm
1
gm
6
), (4)
and with an equivalent series resistor:
R
SEQ
=1/(
gm
1
gm
6
r
B
). (5)
Therefore, we have
z
OH
(
s
)
=
sr
B
C
B
+
1
s
2
r
B
C
L
C
B
+
sC
L
+
sgm
2
r
B
C
B
+
gm
1
gm
6
r
B
+
gm
2
,
(
6
)
Due to gm
1
gm
6
r
B
>>gm
2
, z
O
(s) resonates at:
ω
R
=
gm
1
gm
6
r
B
+
gm
2
r
B
C
B
C
L
≈
1
r
B
C
B
gm
1
r
B
gm
6
C
L
=
gm
1
gm
6
C
B
C
L
=
1
L
OEQ
C
L
,
(
7
)
Q
R
=
r
B
C
L
+
gm
2
r
B
C
B
gm
1
gm
6
C
B
C
L
=
gm
2
r
B
C
B
C
L
C
L
+
gm
2
r
B
C
B
gm
1
r
B
gm
6
gm
2
,
(
8
)
and has a resonated impedance:
&LeftBracketingBar;
z
OH
(
j
ω
R
)
&RightBracketingBar;
=
(
1
C
L
+
gm
2
r
B
C
B
)
C
B
C
L
gm
1
gm
6
gm
1
gm
6
r
B
2
C
B
C
L
+
1
.
(
9
)
If
gm
1
gm
6
r
B
2
C
B
C
L
⪢
1
,
we have:
&LeftBracketingBar;
z
OH
(
j
ω
R
)
&RightBracketingBar;
≈
r
B
C
B
C
L
+
gm
2
r
B
C
B
,
(
10
)
if gm
2
r
B
C
B
>>C
L
, we have
&LeftBracketingBar;
z
OH
(
j
ω
R
)
&RightBracketingBar;
≈
1
gm
2
.
(
11
)
From the above analysis, it is known that the compensation capacitor C
F
in the operational amplifier will cause a gyration effect, so that the internal parasitic capacitance C
B
=C
DB4
+C
DB5
+C
GD4
+C
GD5
+gm
6
r
O
C
GD6
is gyrated to be the inductance in the output impedance. Therefore, the resonated output impedance |Z
OH
(j&ohgr;
R
)| always induces a peak gain on a operational amplifier around several 1 MHz to several 10 MHz. As a result, the gain margin of the operational amplifier is insufficient, or even becomes negative, which will cause a serious problem of oscillating. In general, to avoid this problem, it is necessary to design a very low gain margin for the differential amplifier at the output stage of the operational amplifier. However, such a design will cause various problem such as greatly decreasing the gain bandwidth and increasing the DC offset.
In Japan Patent publication No. 09-01823, there is disclosed an operational amplifier circuit which may alleviate the aforementioned problem by reducing the equivalent value of r
B
. However, such a circuit will cause a problem of insufficient output driving ability, and thus the improvement is limited.
Therefore, it is desirable for the above conventional circuit to be improved so as to mitigate and/or obviate the aforementioned problems.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide a complementary metal oxide semiconductor class AB amplifier for achieving the purposes of saving power and having a large driving capability without sacrificing the gain bandwidth.
In accordance with one aspect of the present invention, there is provided a CMOS class AB amplifier having an adaptive level shift circuit, a compensation capacitor and an output transistor pair to receive an output of a differential amplifying circuit for being provided with a DC bias and a DC amplifying effect by the adaptive level shift circuit, phase compensated by the compensation capacitor, and driven by the output transistor pair. The adaptive level shift circuit comprises: a current mirror circuit having a first NMOS transistor and a second NMOS transistor, each having a gate connected to one another; a NMOS diode transistor having a gate and a drain connected to the gate; a NMOS switch transistor having a source connected to a drain of the second NMOS transistor of the current mirror circuit, a drain connected to a drain of the first NMOS transistor of the current mirror circuit and a source of the NMOS diode transistor, and a gate connected to the gate and drain of the NMOS diode transistor; a PMOS input amplifier transistor having a drain connected to the drain of the NMOS diode transistor; and, a PMOS current source transistor having a drain connected to the source of the NMOS switch transistor.
In accordance with another object of the present invention, there is provided a CMOS class AB amplifier having an adaptive level shift circuit, a compensation capacitor and an output transistor pair to receive an output of a differential amplifying circuit for being provided with a DC bias and a DC amplifying effect by the adaptive level shift circuit, phase compensated by the compensation capacitor, and driven by the output transistor pair. The adaptive level shift circuit comprises: a current mirror circuit having a first PMOS transistor and a second PMOS transistor, each having a gate connected to one another; a PMOS diode transistor having a gate and a drain connected to the gate; a PMOS switch transistor having a source connected to a drain of the second PMOS transistor of the current mirror circuit, a drain connected to a drain of the first PMOS transistor of the current mirror circuit and a source of the PMOS diode transistor, and a gate connected to the gate and drain of the PMOS diode transistor; a NMOS input amplifier transistor having a drain connected to the drain of the PMOS diode transistor; and, a NMOS current source transistor having a drain connected to the source of the PMOS switch transistor.
REFERENCES:
patent: 5212455 (1993-05-01), Pernici et al.
patent: 5789980 (1998-08-01), Nagata et al.
patent: 5907259 (1999-05-01), Yamada et al.
patent: 6163217 (2000-12-01), Matsubara et al.
Bacon & Thomas PLLC
Choe Henry
Lee Benny
Sunplus Technology Co. Ltd.
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