Complementary metal-insulated semiconductor memory decoder

Details Complementary metal-insulated semiconductor memory decoder Complementary metal-insulated semiconductor memory decoder

1981-12-23

1984-06-19

Popek, Joseph A.

Static information storage and retrieval

Addressing

307449, G11C 1140

Patent

active

044556292

ABSTRACT:
A complementary metal-insulated semiconductor (CMIS) which is useful for a highly integrated large-capacity ROM or RAM. The CMIS memory decoder specifies each set of 2.sup.m (m is positive integer) word lines of a memory to be accessed by the CMIS memory decoder. The CMIS memory decoder includes both 2.sup.m CMIS inverters per each set of the 2.sup.m word lines and also 2.sup.m -1 pull-down transistors per each word line, the pull-down transistors being connected between ground and the corresponding word lines, the remaining 2.sup.m -1 word lines being connected to these pull-down transistors at their gates.

REFERENCES:
patent: 3825888 (1974-07-01), Kawagoe
patent: 3909808 (1975-09-01), Cochran et al.
patent: 4063118 (1977-12-01), Nishimura
patent: 4195238 (1980-03-01), Sato
patent: 4275312 (1981-06-01), Saitou et al.
Minato et al., "2K.times.8 Bit Hi-CMOS Static RAM's", IEEE Journal of Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, pp. 656-660.

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