Complementary logic input parallel (CLIP) logic circuit family

Details Complementary logic input parallel (CLIP) logic circuit family Complementary logic input parallel (CLIP) logic circuit family

1991-01-31

1993-09-21

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307449, 307448, H03K 19003, H03K 19017, H03K 19094, H03K 1704, H03K 1920

Patent

active

052472124

ABSTRACT:
A high speed low Capacitance Complementary Logic Input Parallel (CLIP) logic family includes an FET driving stage, a complementary FET inverter, and at least one gating FET. The dimensions of the gating FET are controlled relative to the dimensions of the driving stage FETs to provide a high speed logic circuit. AND and OR CLIP logic circuits may be provided. A clocked CLIP logic circuit may be provided by adding a clocking FET. A latching clocked CLIP logic circuit may also be provided by adding a latching FET. In the latching clocked CLIP logic circuit, the gate output is latched so that it does not change during the clock period regardless of changes in the logic inputs of the circuit. The speed of the CLIP logic circuits may be further increased by including germanium in the channel of its P-channel FETs to thereby increase carrier mobility in the P-channel FETs. The N-channel FETs are free of germanium. The internal capacitance of the CLIP logic circuits is also decreased by using common diffusion regions in the integrated circuit for pairs of driving stage FETs. Common source and/or common drain diffusion regions may be used.

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