Complementary junction field effect transistors

Details Complementary junction field effect transistors Complementary junction field effect transistors

1999-12-09

2001-10-23

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S268000, C257S272000, C257S263000, C257S264000, C257S274000, C257S277000

Reexamination Certificate

active

06307223

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the Complementary Junction Field Effect Transistors (CJFETs) that can be used in high speed electronic circuits for low voltage and/or large current applications. This invention is using enhancement mode or normally “off” Junction Field Effect Transistors with an N-channel JFET and a P-channel JFET in series connection. The gates of both normally “off” JFETs are connected together. This forms the Complementary Junction Field Effect Transistors.
2. Description of the Prior Art
The concept of Junction Field Effect Transistor (JFET) is well known since the invention of the junction transistors. Junction Field Effect Transistor is a majority carrier device, it offers high frequency response. However, the normally “off” JFET is using a P-N junction as the gate so that it is effective to turn-off the device by reverse bias the gate. This normally “on” or depletion mode FET is available in the market. Without readily available normally “off” or enhancement mode version, JFETs are not widely used as the MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). In order to make the normally “off” FET, the distance between the gates must be smaller enough so that the depletion regions from both gates fill up the conduction channel. No current is flow when the gate is at zero bias. This means that at forward bias above the threshold voltage, the depletion region is smaller enough, the conduction channels between source and drain are open.
S. M. Sze has clearly described this concept in page 323, “Physics of Semiconductor Devices”, 2
nd
edition, John Wiley & Son, 1981. The symbols for N-type and P-type normally “on” and normally “off” JFET and MESFET are illustrated. However, in this book, the application of normally “off” JFET is described for high speed and low power application. Since the original device structure has very long channel length that limits the current carrying capability and high on resistance.
This inventor, Ho-Yuan Yu, has filed the following inventions: 1) “Low On Resistance Transistors and the Method of Making”, filed in Patent Office of Disclosed Document Program, Sep. 24, 1998, #444899, has disclosed the device structures for high current and low on resistance applications. This is a normally “on” JFET. 2) “Novel Structure of JFETs for Low Voltage Application”, filed in Patent Office of Disclosed Document Program, Sep. 17, 1998, #444874, disclosed the device structures of normally “off” JFETs for low voltage and high current applications. Above two documents have combined together to file a provisional patent application, #60/115,009 on Jan. 6, 1999 and filed utility patent application on Oct. 28, 1999. Present invention is using normally “off” JFETs with the structures shown in #60/115,009 and additional structures shown in this patent application with both N-channel and P-channel JFETs to perform the complementary circuitry function that can be used in high speed, low voltage and high current applications.
SUMMARY OF THE PRESENT INVENTION
This invention comprises a pair of N-channel and P-channel normally “off” or enhancement mode Junction Field Effect Transistors (JFETs) in series connection . The gates of both devices are connected together. Since the normally “off” JFET is using a forward bias of gate voltage in respect to the source and drain to turn on the device, the voltage range of the gate is normally less than +/−0.75V. Otherwise, the gate will draw large amount of current. A current limiting device to the gate can also be built in for Complementary Junction Field Effect Transistor structures. The threshold voltage for the gate is usually set around 0.2 V to 0.3V depending on the operating temperatures and applications. The threshold voltage of 0.2 V to 0.3V can allow the device to be operated up to 200 degree C. Actually, the gate voltage of 0.5V is sufficient to turn on the device and allow large amount of current flow from the source to drain or vise versa. The forward bias current of the gate at 0.5V is in the range of 3 to 5 orders of magnitude smaller than the source and drain current. This kind of device offers very attractive large current gain.
Normally “off” or enhancement mode JFETs can be built by several device structures. The original JFET structure is using double diffused method to create the conduction channel with source and drain located at the ends of the channel and the gate is located on the top of the conduction channel. This kind of structure has long channel length and it does not offer high current density and high packing density of the device on silicon chip. The device structures disclosed in the Inventor's previous patent application are suitable for high current and low voltage application. Additional device structure on SOI wafers is also disclosed in this patent application.
The Complementary Junction Field Effect Transistors can be built either with the discrete devices, the integrated device, and the device built in standard CMOS or SOI process that can be used as the building block of the Complementary JFETs for modern circuitry.


REFERENCES:
patent: 5945699 (1999-08-01), Young

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