Patent
1980-04-07
1981-11-10
Larkins, William D.
357 15, 357 23, 357 38, H01L 2704, H01L 2978, H01L 2956
Patent
active
043001521
ABSTRACT:
A CMOS integrated circuit structure which is not susceptible to latchup utilizes insulated-gate field-effect transistors having Schottky barrier source and drains (SB-IGFET). In the preferred embodiment, the n-channel device of an adjacent complementary pair of transistors in a CMOS circuit is provided with diffused source and drain while the p-channel device of the pair is provided with PtSi-Si Schottky barrier contact source and drain. Such a structure completely eliminates the parasitic pnpn structure which causes the latchup problem in conventional CMOS structures.
REFERENCES:
patent: 3590471 (1971-07-01), Lepselter et al.
patent: 3708360 (1973-01-01), Wakefield, Jr. et al.
patent: 4015147 (1977-03-01), Davidson et al.
patent: 4035826 (1977-07-01), Morton et al.
patent: 4053925 (1977-10-01), Burr et al.
patent: 4137545 (1979-01-01), Becke
patent: 4152717 (1979-05-01), Satou et al.
patent: 4203126 (1980-05-01), Yim et al.
Ames et al., IBM Technical Disclosure Bulletin, vol. 9, No. 10, Mar. 1967, p. 1470.
Dennehy, "Non-Latching Integrated Circuits", RCA Technical Note #872, Feb. 12, 1971.
Proc., IEEE, Aug. 1968, pp. 1400-1402.
Bell Telephone Laboratories Incorporated
Larkins William D.
Torsiglieri Arthur J.
LandOfFree
Complementary field-effect transistor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Complementary field-effect transistor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary field-effect transistor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2364703