Complementary field effect devices for eliminating or reducing d

Details Complementary field effect devices for eliminating or reducing d Complementary field effect devices for eliminating or reducing d

1997-04-28

2000-04-25

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257350, 257377, 257383, 257384, 257393, 257903, 257904, H01L 27108, H01L 2701, H01L 2711

Patent

active

060547227

ABSTRACT:
A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

REFERENCES:
patent: 4814841 (1989-03-01), Masuoka et al.
patent: 5331170 (1994-07-01), Hayashi
patent: 5625200 (1997-04-01), Lee et al.
"Semiconductor Memory Process Integration" pp. 575 and 576, 1990.

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